In 2010, the RISC-V architecture was born at the University of California, Berkeley. Thanks to its streamlined and efficient advantages, it quickly gained support from academia. After nearly a decade of development, the RISC-V architecture has received widespread recognition in both academia and industry, and is also embraced by many chip companies in China. Today, numerous tech companies in Silicon Valley have developed various products integrated with RISC-V processors. With the RISC-V ecosystem maturing, processors based on RISC-V will surely see widespread application in the future.
Chip Architecture Diagram C910
The RISC-V CPU Design Practice Course launched in collaboration between Moores Elite E-Class and Chip Technology is an advanced specialized course in the field of IC design engineering, focusing on the microarchitecture design of the open-source RISC-V E203 CPU core. The course covers 20% foundational theory of computer architecture, 70% on the design methodology of the Hummingbird E203 CPU core, and the remaining 10% briefly introduces related knowledge such as RISC-V instruction architecture, high-level language programming, compilation processes, machine execution principles, microarchitecture design, RTL implementation, and simulation testing.
Hummingbird E203
This course deeply integrates theoretical knowledge of computer architecture with engineering practice of the Hummingbird E203 CPU core, striving to enable students to quickly and thoroughly master embedded CPU core design capabilities, laying a solid foundation for future large-scale SoC design and high-performance core design.
Target Audience
Digital circuit design engineers with IC design experience
Senior undergraduate and graduate students majoring in electronics
Working engineers interested in entering the digital IC design industry
Those wishing to master the open-source RISC-V CPU core design methodology
Course Benefits
Hands-on guidance in designing an open-source RISC-V CPU core
Accumulation of a complete RISC-V CPU core design project experience
7 x 24-hour project server practice
Proficiency in hardware-software co-design methodology
Collaboration with Chip Technology: Hummingbird E203 source code download + FPGA development board
FPGA Display
Course Outline
|
No. |
Details |
Hours |
|
1 |
History of Architecture |
1 |
|
2 |
RISC-V ISA |
1 |
|
3 |
Introduction to Basic Experimental Environment |
1 |
|
4 |
Hummingbird E203 SOC Architecture |
1 |
|
5 |
Hummingbird E203 CORE Architecture |
1 |
|
6 |
RISC-V Basic Experiment 1 |
1 |
|
7 |
E203 Arithmetic/Memory Access Instruction Implementation |
1 |
|
8 |
E203 Branch/CSR Instruction Implementation |
1 |
|
9 |
RISC-V Basic Experiment 2 |
1 |
|
10 |
E203 Peripheral Resources |
1 |
|
11 |
RISC-V Basic Experiment 3 |
1 |
|
12 |
Introduction to XuanTie 910 Microarchitecture |
1 |
Instructor Profile
Teacher Li:
Engaged in IC design for 8 years, CPU chip design engineer at the 58th Research Institute of China Electronics Corporation, senior chip design engineer at the Institute of Microelectronics, Chinese Academy of Sciences.
Project Experience:
1. Development of embedded teaching experimental box
2. Performance evaluation of on-chip network systems
3. Parallel optimization of algorithms for a certain model detector and FPGA implementation
4. Microarchitecture design of initialization unit, encryption/decryption unit, TAP system unit for a certain model detector
5. Improvement of algorithms for FPU of a certain model superscalar processor, simulator development, performance analysis
6. Research on floating-point algorithms for superscalar processors
7. Microarchitecture design and implementation of HDMI-CEC IP
8. Basic training for embedded processors
9. Basic training for digital front-end design
10. Translation of the superscalar processor design book
Learning Method
Online live streaming / offline teaching + real-time Q&A + practical exercisesCourse Start: January 20, 2024 (Saturday) 09:00
Class Schedule
Saturday + Sunday: 09:00-12:00 in the morning, 14:00-17:00 in the afternoonEarly bird discounts are available for registrations before the course start date, details as follows:
| First 30 participants | Offline with VNC (4 weeks) + FPGA development board | 1980 RMB |
| Online with VNC (4 weeks) + without FPGA development board | 1980 RMB | |
| No VNC, no FPGA development board | 1580 RMB |
Note: VNC is a remote server that allows viewing, compiling source code, and performing simulations
Registration Inquiry
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E-Class Network (www.eecourse.com) is a professional integrated circuit education platform under Moores Elite, dedicated to cultivating high-quality professionals in the semiconductor industry. The platform is oriented towards the job requirements of integrated circuit companies, providing a practical training platform that aligns with the corporate environment, quickly training students to meet corporate needs.
E-Class Network has a mature training platform, a comprehensive course system, and strong teaching resources, planning 168 high-quality semiconductor courses in China, covering the entire integrated circuit industry chain, and has 4 offline training bases. To date, it has deeply trained a total of 15,367 people, directly delivering 4,476 professionals to the industry. It has established in-depth cooperative relationships with 143 universities and has held 240 corporate-specific IC training sessions.