On July 17, 2025, the 2025 RISC-V China Summit officially opened in Zhangjiang, Shanghai, China. Hu Zhenbo, the founder of Chiplet Technology, delivered a keynote speech titled “The Process and Outlook of RISC-V Commercialization IP” at the conference.
The RISC-V Foundation was established in 2015, and Hu Zhenbo is one of the earliest individuals in China to engage with RISC-V. During that time, he worked on numerous open-source projects related to RISC-V in his spare time and authored one of the earliest books on RISC-V in China. In 2018, based on his previous experience with RISC-V, Hu Zhenbo founded Chiplet Technology, turning his interest into a lifelong career.
Hu Zhenbo, founder of Chiplet Technology
In the seven years since its establishment, Chiplet Technology has focused on the IP field, which is a highly challenging niche market for startups. According to Hu Zhenbo, “We have a very small team, only a fraction of the manpower compared to our international peers, and our funding is also only a fraction of theirs. We started relatively late, so we also have only a fraction of the time. However, we have achieved several accomplishments and have realized relatively high output efficiency. Our per capita IP output value is very high, and we have established a unique R&D system and business methodology.”
As of now, Chiplet Technology has entered the first tier of RISC-V IP and is one of the most comprehensive suppliers in the field. Hu Zhenbo humorously remarked, “We have more IP than people in the company.”
In terms of CPU IP, Chiplet Technology has developed six series from N100 to UX100, including over 20 CPU IPs across four general-purpose levels (N, NX, U, UX) and four specialized levels (NI, NA, NI, ND); in terms of bus IP, it has two series: Bus Fabric and NoC; for SoC and accelerator IP, it has created over 30 SoC IPs and algorithm accelerators such as SDIO, SPI, USART, and FFT; the interface IP controllers include USB2.0 controllers, GMAC controllers, PCIe controllers, DDR controllers, and more; in terms of encryption and wireless IP, it covers national and commercial encryption standards, as well as wireless algorithm IP.
Can the business model of IP be established? Hu Zhenbo believes this mainly depends on three fundamental elements: first, consensus or standard technology protocols; second, widespread and fragmented market demand; and third, general product forms. RISC-V CPU IP perfectly meets these three elements, but that alone is not enough. The industrialization of RISC-V CPU IP is the first and crucial step in the industry; only with a rich, mature, and reliable commercial IP can subsequent industrial links be empowered. This is a very important closed-loop relationship.
Chiplet Technology’s extensive and comprehensive IP portfolio is indeed laid out around industrial relationships and underlying logic. Different application scenarios have different characteristics and needs, and Chiplet Technology’s IP products are developed according to the corresponding scenarios.
Primarily used in the information security field for national encryption, finance, power grids, and SIM card applications, it features technologies to prevent side-channel attacks, requiring parity protection, consistent instruction execution times, and random instruction injection, among other requirements. The market size is relatively small and fragmented. Since this is a specific scenario, the ecological requirements are not very high, so RISC-V can also implement some quantitative or qualitative custom instruction extensions to meet more secure requirements. Chiplet Technology has launched the NS series, including NS100, NS300, and NS600 in this field.
In the currently booming automotive electronics market, RISC-V also has significant opportunities. RISC-V, being a single instruction set, can effectively overcome the ecological fragmentation caused by closed instruction sets or the coexistence of multiple instruction sets. Additionally, as the software ecosystem becomes increasingly important, a single instruction set can support a unified software ecosystem well. RISC-V, being an open instruction set, can avoid strong single dependencies. Chiplet Technology has launched corresponding IP product lines for the automotive field. Notably, besides Chiplet Technology, chip companies like Ouyue Semiconductor and Silan Microelectronics have also introduced automotive-grade chips based on RISC-V. Great Wall Motors’ Nanjing Zijing Semiconductor has announced that its automotive-grade RISC-V MCU, Zijing M100, is about to enter mass production.
In the current artificial intelligence field, RISC-V is widely present in AI chips. Among multi-core solutions, RISC-V is also a very preferred option. Additionally, in NPU-based computing chips, there is a need for general computing capabilities with standard ecosystems, especially for Vector VPUs. Among these solutions, RISC-V is almost the mainstream option. Chiplet Technology’s IP can be utilized here, especially the NI900 series, which is a representative of high-performance parallel computing IP, favored by many local developers.
Currently, in specific niche areas, the software ecosystem is relatively easy to land due to its strong closure and clear demand, making RISC-V more viable. However, due to the characteristics of niche markets, the overall market size is limited. Hu Zhenbo believes that in specific niche areas, Chiplet Technology’s experience is not universally applicable. Chiplet has achieved relatively leading results in several specialized RISC-V CPU IP fields, relying on its self-developed system. This path has certain characteristics and is not universally replicable.
In contrast to specific fields is the so-called general RISC-V CPU IP market, which refers to CPU IP with standardized interfaces and general specifications that can be applied across fields, rather than being limited to a specific type of “industry” or “application.” From the perspectives of market capacity, customer base, lifecycle, and ecosystem development, general IP is undoubtedly a more sustainable and scalable market direction.
The earliest commercialization breakthrough of RISC-V originated from low-power scenarios, as its simplified instruction set, customizable architecture, and high configurability make it naturally suitable for resource-constrained embedded and control chips. It has already achieved large-scale deployment in various low-power application fields, including IoT devices, smart homes, wearables, low-power sensor nodes, and wireless connection modules. The shipment volume of RISC-V architecture chips has significantly increased, with low-power SoCs dominating, accounting for the largest proportion of RISC-V’s overall shipment volume. At certain relatively simple RISC-V CPU IP levels (especially those without DSP, floating-point, or cache), there is potential for self-developed commercial balance.
Furthermore, RISC-V CPU IP is also extending towards higher performance scenarios, competing with Arm’s A76 and A78 levels. The RVA23 Profile, representing the architectural specification system, marks a new stage in the standardization process of RISC-V in 64-bit computing platforms. In the ultra-high-performance field, RISC-V also has opportunities and potential, targeting desktop and server domains. On the hardware side, ultra-high-performance RISC-V CPU IP has engineering possibilities. On the software ecosystem side, the RISC-V architecture and foundation standards are also steadily advancing. Chiplet Technology’s 2000 series, aimed at the server field, is currently in the R&D stage. However, the overall number of IP customers in this field is relatively small, and the RISC-V CPU IP in this field is primarily self-developed; the focus at this level should not be on IP but on chips.
At the end of his speech, Hu Zhenbo also made several forecasts regarding the development of the RISC-V commercial IP industry: ① RISC-V will not disrupt ARM in the short term but will present a complementary relationship, with a future of long-term coexistence and healthy competition serving the market together. ② RISC-V should also respect commercialization; like other standard protocols, RISC-V needs to rely on a stable and deliverable commercial IP system to endure. ③ The commercial RISC-V IP is currently in a stage of “a hundred boats competing to cross the river”; as the market and ecosystem mature, it will gradually move towards industrial concentration, but it will not form a monopoly. ④ The real breakthrough of the RISC-V ecosystem comes from large-scale applications of RISC-V in general MCUs, MPUs, APs, CPUs, and other core computing platforms. ⑤ The RISC-V ecosystem and commercialization are still in the early stages, and one must be prepared for a very long cycle; it is not something that can be achieved overnight, and one should avoid some short-sighted thinking.
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