The wind is favorable for setting sail; one does not wait for the whip to spur the horse! Time flies, and 2025 is already half over. In this half year, all staff at Zhongke Core have anchored their goals and moved forward with determination, deeply studying and implementing the spirit of the 20th National Congress of the Communist Party, with the courage to be pioneers and a pursuit of excellence, truly grasping practical work to fully promote the high-quality completion of scientific research and production tasks.WeChat public account now launchesthe “Mid-Year Efforts” column, gathering frontline dynamics, recording moments of unity and cooperation, and showcasing the spirit of Zhongke Core employees who are striving and continuing to fight!
Focusing on the goal of empowering intelligent computing,the laboratory design centerintelligent algorithm teamis carrying outNPU architecture and software stack technical breakthroughs.Focusing onalgorithm deployment and computational efficiency issues on edge systems, we are rapidly advancing the full-stack capability construction from underlying hardware and software architecture to system integration, and have initially exploredaself-developed technical route suitable for deploying large models on heterogeneous computing platforms.
Research Application Needs Defining Intelligent Computing Chips
The team has successively connected with key research institutes and well-known universities in the fields of optoelectronics, underwater acoustics, etc.,to understand the image, communication, underwater acoustics, and other modal processing systems currently deployed,research mainstream model structures on the algorithm side, and sort out the actual computational bottlenecks and execution characteristics in edge deployment, providing direct input for architecture design and software definition, and offering a demand anchor point for chip development based on real scenarios.At the same time,the team adheres to the concept of collaborative design of software and hardware, during the chip architecture definition phase,analyzing the performance of typical tasks on the edge,facing the two types of performance bottlenecks: “compute-limited” and “bandwidth-limited“, proposing hardware design strategies such as multi-core scheduling and dual-channelDMA concurrent loading. Currently, on the software side, through the “operator compilation-data address planning-instruction generation” toolchain development, we have completed the adaptation loop with the underlying architecture of the NPU, forming a collaborative R&D model of “defining architecture based on requirements, and then deriving deployment software from the architecture“.
Self-Developed Software Toolchain Empowering Edge Computing
The team has defined the autonomousNPU architecture based on demand, completing operator definition, model numerical simulation,ONNX framework model compilation, instruction assembly, and other layered toolchain construction. Over the course of six months, we efficiently completed the definition and verification of over40 highly reusable NPU operators, forming software and hardware deployment solutions for three types of typical tasks, with performance indicators meeting actual application needs.At the same time, in the context of the rapid development of multi-modal fusion large models, the team has also completed the design of a heterogeneous hybrid computing system based on the self-developedCIP chip interconnection protocol for “CPU+FPGA+NPU”, establishing a system-level computing platform that supports large model inference and defining and completing the software stack for heterogeneous platforms.In addition, facing the trend of lightweight edge deployment, we innovatively proposed a runtime dynamic rescheduling mechanism based onCPU to compress the instruction space of ~TB level models to ~GB range under limited resources on the edge, effectively solving the common instruction space expansion bottleneck faced by similar systems.
The team has always adhered to the development idea of “application demand-driven, software-defined architecture”, extracting common problems based on users’ actual needs, defining software and hardware architecture starting from system bottlenecks, firmly binding to real system scenarios, avoiding the common dilemmas of “technical idling” and “algorithm detachment”. In the future, the team will accelerate application validation after the NPU chip returns in the third quarter, continuing to focus on core technologies such as large models, edge collaboration, and chip interconnection, enhancing the collaborative design capability of software and hardware, and contributing safe and reliable technical support for domestic intelligent computing chips.
Reporter/Cheng Hu