First, the answer: Inside the MCU chip, a resistor (or an equivalent “weak connection”) is placed between VSS and VSSA, rather than a direct short circuit or complete open circuit. This is based on the core ideas of “single-point grounding” and “noise isolation”, but also requires additional consideration of the physical realities and reliability of chip manufacturing.

1. Why can’t they be directly connected (short-circuited) internally?

If VSS and VSSA are short-circuited on the silicon chip with a wide metal line, it is equivalent to building a high-speed highway for digital noise to directly reach the analog core inside the chip.

• Noise cannot be isolated: The significant ground bounce noise generated by the digital subsystems (CPU, bus, digital peripherals) will directly couple to the reference ground of the analog area (such as ADC, PLL, analog comparators).

• Analog performance degradation: This direct noise injection will severely reduce the performance of the analog circuits, leading to:

• Decreased ADC accuracy: The lower bits of the conversion results will fluctuate, and the signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) will worsen.

• Increased PLL jitter: The clock output becomes unstable, affecting system timing.

• Amplifier offset: Comparators or operational amplifiers may produce false judgments due to noise.

• Loss of design flexibility: Once directly connected internally, board-level designers can no longer optimize the grounding method based on the actual application needs (sensitivity to noise).

2. Why can’t they be completely separated (open circuit) internally?

Completely isolating VSS and VSSA inside the chip sounds ideal, but it leads to a series of more serious problems:

• Floating potential and ESD risk: During manufacturing, packaging, soldering, or normal operation, two completely isolated ground networks may develop different potentials due to external interference or electrostatic discharge (ESD). A significant potential difference may break down the delicate gate oxide layer of analog transistors,leading to permanent damage to the chip.

• Signal integrity disaster: All internal signals connecting digital and analog modules (e.g., signals from the digital part controlling the ADC start) will have their return current paths forced to bypass this “break zone,” forming large loops that generate strong electromagnetic interference (EMI) and cause signal ringing and edge degradation.

• Leakage current causing offset: Even without external interference, there are small leakage currents inherent in semiconductors. These leakage currents may cause the potential of VSSA to slowly drift relative to VSS, leading to the operating point (bias voltage) of the analog circuit deviating from the design value, resulting in malfunction.

3. Solution: “Weak connection” or “lossy connection” inside the chip

Therefore, the compromise solution for MCU designers is to establish a controllable, high-impedance connection path inside the chip. This path is typically not a visible resistor but is achieved through the following methods:

1. Long and thin polysilicon resistor: In CMOS technology, it is very easy to create a high-resistance resistor, requiring only a long and thin piece of polysilicon. Its function is similar to that of a 0-ohm resistor or ferrite bead at the board level:

• Providing a DC path: Ensures that VSS and VSSA are at the same potential in DC state, eliminating the risk of floating potential and providing a safe discharge path for ESD currents (although the impedance is high, ESD protection circuits are usually designed to handle this situation).

• Suppressing AC noise: High resistance presents a high impedance to high-frequency noise currents,greatly attenuating the noise energy from digital ground to analog ground. Although not as efficient as board-level ferrite beads, it serves as the first and crucial isolation barrier inside the chip.

Back-to-back connected ESD protection devices: Sometimes, this connection is integrated into the ESD protection network, using some nonlinear devices that present high impedance under normal voltage but quickly conduct when encountering high voltage (such as ESD) to provide protection.

Collaboration between chip design and board-level design

The existence of this “weak connection” inside the chip does not replace best practices in board-level design. On the contrary, they work in synergy:

• Internal chip resistance: Providesthe most basic protection. It prevents the chip from being damaged or completely non-functional due to floating potential in the worst-case scenario (e.g., if the board-level designer forgets to connect VSS and VSSA). It handles the most basic noise coupling generated inside the chip.

• Board-level single-point connection: Board-level designers stillmust connect VSS and VSSA at a single point on the PCB, close to the MCU power pins, using a 0-ohm resistor or ferrite bead. This is the ultimate and most effective noise isolation solution. This connection provides a low-impedance DC path and, together with the PCB ground plane, offers the optimal path for return currents, while the board-level ferrite bead can more effectively filter high-frequency noise.

Conclusion

Solution	Advantages	Disadvantages	Conclusion
Internal direct connection	None	Digital noise directly contaminates the analog ground, degrading analog performance	Not advisable
Completely separated internally	Ideal perfect isolation	1. Floating potential leads to ESD breakdown risk 2. Return current path issues 3. Leakage current causing offset	Extremely dangerous, not advisable
Weak resistive connection internally	1. Provides DC path, preventing floating potential 2. Suppresses AC noise, serving as the first isolation barrier 3. Provides ESD protection path 4. Maintains design flexibility	Isolation effect is not as good as board-level ferrite beads	Optimal compromise solution, standard design for professional MCUs

Therefore, the resistor between VSS and VSSA inside the MCU chip is a careful compromise made by chip designers after a deep understanding of noise, reliability, and manufacturing processes. It ensures the robustness of the chip at the most basic level while providing board-level engineers with the space to further optimize system performance.

Previous articles:

What is the typical yield of the MCU you use?

Introduction to wire bonding inside the MCU

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