Introduction: Why Do We Need Makefile?

In Windows IDEs, we can simply click the “Build” button to complete the compilation, but behind large projects often lies complex build logic. Makefile is the core tool for achieving automated builds in Linux/Unix environments, acting like a precise conductor that coordinates:

• Optimization of compilation order
• Incremental compilation (only recompiling modified files)
• Dependency management
• Cross-platform builds

Core Concepts: The Three Elements of Makefile

1. Target + Prerequisites + Command

target: prerequisites
	command

• Target: The file to be generated (such as an executable file or .o file) or a virtual target (like clean)
• Prerequisites: The files required to generate the target
• Command: The actual Shell command to be executed (must start with a TAB)

2. Workflow Analysis

1. Locate the Makefile/makefile file
2. Execute the first target (default target)
3. Recursively check dependencies:

• If the dependency file is newer than the target, execute the command
• If the target does not exist, execute the command directly

Finally generate the top-level target

Practical Case: Writing a Makefile from Scratch

Basic Version (Explicit Dependencies)

edit: main.o kbd.o command.o
	cc -o edit main.o kbd.o command.o

main.o: main.c defs.h
	cc -c main.c

kbd.o: kbd.c defs.h
	cc -c kbd.c

clean:
	rm -f edit *.o

Evolved Version (Using Variables)

OBJ = main.o kbd.o command.o
CC = gcc

edit: $(OBJ)
	$(CC) -o $@ $^

%.o: %.c
	$(CC) -c $< -o $@

.PHONY: clean
clean:
	rm -f edit *.o

Key Improvements:

• <span><span>OBJ</span></span> variable centrally manages target files
• <span><span>CC</span></span> variable centralizes compiler configuration
• Pattern rules<span><span>%.o: %.c</span></span> automatically derive compilation commands
• <span><span>.PHONY</span></span> declares phony targets (not corresponding to actual files)

Detailed Explanation of Core Features

1. Automatic Variable Magic

Variable	Meaning	Example Value
<span><span>$@</span></span>	Current target file name	<span><span>edit</span></span>
<span><span>$^</span></span>	List of all dependency files	<span><span>main.o ...</span></span>
<span><span>$<</span></span>	First dependency file	<span><span>main.c</span></span>

2. Implicit Rules

Make has built-in common compilation rules:

.c.o:
	$(CC) -c $(CFLAGS) $<

Equivalent to the automatically derived:

%.o: %.c
	$(CC) -c $< -o $@

3. Phony Targets (.PHONY)

• Avoid conflicts with files of the same name
• Force command execution (even if a file of the same name exists)
• Typical applications:<span><span>clean</span></span>, <span><span>install</span></span>, <span><span>test</span></span>

Troubleshooting Common Issues

Q1: Did not recompile after modifying header files?

# Explicitly declare header file dependencies
main.o: defs.h buffer.h

Q2: Clean rule not working?

# Correct syntax (place clean at the end)
.PHONY: clean
clean:
	rm -f $(TARGET) $(OBJ)

Q3: Parallel compilation acceleration

make -j4 # Use 4 threads for compilation

Conclusion: The Value of Makefile

• Efficiency improvement: Reduces over 90% of redundant compilation time
• Code maintenance: Centralized management of compilation configuration
• Cross-platform: Achieve one-click builds with Autotools
• Engineering: The foundation for building projects with millions of lines of code

Mastering Makefile is not just about mastering a tool, but understanding the art of software building. The evolution from manually typing commands to automated builds represents the transformation of programmers from “slash-and-burn” to “industrial production.” In the next phase, we can explore:

• Automatic dependency generation (using the -MMD option)
• Conditional compilation and platform adaptation
• Integrating CMake/Autotools build systems

Now, open your editor and write your first Makefile for the next project!