Three Questions About Makefile in Linux

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• What is a makefile?

A makefile is a file used to describe how to compile and link a program. It contains rules for compilation and linking, dependencies, target files, and other information. By writing a makefile, you can automate the compilation and linking of programs, improving development efficiency. A makefile typically includes the following content:

1. Rules: Specifies how to compile and link target files.

2. Variables: Defines some variables for use in the rules.

3. Dependencies: Specifies which source files the target files depend on.

4. Target files: Specifies the target files to be generated.

The rules in a makefile usually follow this format: target: prerequisites
<tab> command

Where target is the target file to be generated, prerequisites are the source files that the target file depends on, and command is the compilation and linking command. For example, the following makefile defines a target file named “hello” that depends on the source file “hello.c” and uses the gcc compiler for compilation and linking:

hello: hello.c
	gcc -o hello hello.c

When the user executes the make command, the make tool reads the makefile and generates the target file according to the rules. If the target file does not exist or the source files it depends on have changed, the make tool will automatically execute the corresponding commands to regenerate the target file.

• How to write a makefile?

Writing a makefile requires following certain rules and syntax. Here are some basic steps and methods for writing a makefile:

1. Determine the target files and dependency files: Before writing a makefile, you need to determine the target files to be generated and their dependent source files. For example, if you want to compile an executable file named “hello”, its dependency files might be “hello.c” and “hello.h”.

2. Write rules: The core of writing a makefile is writing rules, which specify how to compile and link the target files. Rules usually follow this format: target: prerequisites
<tab> command

Where target is the target file to be generated, prerequisites are the source files that the target file depends on, and command is the compilation and linking command. For example, the following rule specifies how to compile and link the “hello” executable file:

hello: hello.c
	gcc -o hello hello.c

3. Define variables: When writing a makefile, you can use variables to simplify rules and commands. For example, you can define the name of the compiler as a variable for use in the rules:

CC=gcc
hello: hello.c
	$(CC) -o hello hello.c

4. Write dependencies: When writing a makefile, you need to specify the source files that the target file depends on. Dependencies usually follow this format: target: prerequisite1 prerequisite2 …

For example, the following dependencies specify that the “hello” executable file depends on the source files “hello.c” and “hello.h”:

hello: hello.c hello.h

5. Write target files: When writing a makefile, you need to specify the target files to be generated. Target files usually follow this format: target:

For example, the following target file specifies that the “hello” executable file is to be generated:

hello:

6. Write clean rules: When writing a makefile, you can write clean rules to delete generated target files and temporary files. Clean rules usually follow this format: clean:
<tab> rm -f hello

For example, the following clean rule specifies to delete the “hello” executable file:

clean:
	 rm -f hello

In summary, writing a makefile requires following certain rules and syntax. You need to first determine the target files and dependency files, then write rules, define variables, write dependencies, write target files, and clean rules.

• How does a makefile work?

A makefile is an automation build tool used to automate the compilation, linking, and installation of software. It simplifies the build process in software development by reading the rules and commands in the makefile and automatically executing compilation, linking, and installation operations. The working principle of a makefile is as follows:

1. Read the makefile: The make tool reads the rules and commands in the makefile and executes the corresponding commands according to the rules.

2. Determine the target files: The make tool determines the target files to be generated based on the rules in the makefile.

3. Check dependencies: The make tool checks whether the source files that the target files depend on already exist. If they exist, it skips the compilation and linking operations; if they do not exist, it executes the corresponding compilation and linking operations.

4. Execute commands: The make tool executes the corresponding commands based on the rules in the makefile to generate the target files.

5. Repeat execution: The make tool repeats the above steps until all target files are generated.

As an automation build tool, a makefile simplifies the build process in software development by reading the rules and commands in the makefile and automatically executing compilation, linking, and installation operations.