Learning Makefile

GDB Debugging Tool

Common commands for GDB debugging:

gcc -g main.c -o main

Common commands: help

bt Show the call stack

info locals Show local variables

break main.c:10 Set a breakpoint at line 10

next Execute the next line

list List source code

continue Continue execution

print Print variable value

start Restart program execution

delete Delete breakpoint

frame View current stack frame

search Find variable value

info registers View register values

display Show variable value

x Print memory value

quit Exit

GDB Debugging Mode:

run Run the program

start Restart the program and step through

set follow-fork-mode child Track child processes

Makefile Project Management

Purpose

  1. Automate the compilation process
  2. Save time in compiling projects
  3. Facilitate collaboration among multiple developers
  4. Write once, benefit forever

Basic Syntax

Target: Dependencies Command establishes a relationship tree from top to bottom, executing from bottom to top.

  • Analyze the dependencies between target files
  • Execute commands from bottom to top based on dependencies
  • Determine updates based on modification time being newer than the target
  • If the target has no dependencies, execute the corresponding command to indicate an update

.PHONY is a phony target, not corresponding to a file, will execute commands prefixed with -, ignore errors and continue execution. Commands prefixed with @ will not display the command itself. % is a wildcard.Alldependenciesaremet< First dependency $@ Current target

Functions in Makefile: wildcard Match files, patsubst Replace filenames, subst Replace filenames, patsubst Replace filenames

Example

# Preprocessing, compilation, and linking flags -I for header files
CPPFLAGS= -Iinclude
# Compilation flags -g for debug info, -Wall for warning info
CFLAGS= -g -Wall
# Linking flags -L for library path, -l for library name to specify shared library
LDFLAGS= 
# Compiler type
CC=gcc
#CC=arm-linux-gcc
# Source file list, target file name
src = $(wildcard *.c)
# List of object file names replacing source file names with .o
obj = $(patsubst %.c,%.o,$(src))
# Target file name
target = app
# Default target
$(target):$(obj)
	$(CC) $^ $(LDFLAGS) -o $@
# Compilation rule, automatically generate .o files
%.o:%.c
	$(CC) -c $< $(CFLAGS) $(CPPFLAGS) -o $@
# Phony target, not corresponding to a file, will execute
.PHONY:clean

# Completely clean generated process files
clean:
	-rm -f *.o
	-rm -f app

# Completely clean generated process files and generated configuration files
distclean:
	rm /usr/bin/app
install:
	cp app  /usr/bin

# Test rule, print variable values
test:
	@echo $(src)
	@echo $(obj)

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