Can Programmers Who Don't Understand Makefile Still Write Code?

Introduction: Tired of Typing Compilation Commands? It’s Time to Learn Automation!

Hello everyone, I am Xiaokang!

Last time we talked about GCC, G++, and GDB, clarifying how these tools are used in C/C++ development. With them, you can happily compile and debug your code.

But let me ask you, do you manually type the gcc command every time you compile a project? As the number of project files increases, the command becomes like a tongue twister—long, complex, and prone to errors. Don’t worry, today I will introduce you to a “lazy person’s tool”—Makefile.

The benefits of using Makefile are simple:

Automated code compilation, easy and efficient;
No need to manually type commands, reducing mistakes;
No matter how large the project is, it can handle it all.

Once you learn to write Makefile, you won’t have to worry about the tedious task of compilation anymore! Let’s start from scratch and step by step clarify what it is and how to write it, so you can use it after reading!

1. What is Makefile?

Makefile is a compilation commander, where you write the compilation rules inside, and then with a simple command make, it will automatically complete all compilation tasks according to the rules.

For example, you are the project manager, and Makefile is your notebook, recording the project’s “construction plan”:

The source of each target (like the executable file main);
What commands are needed to generate these targets;
What parts need to be reused (like intermediate files *.o).

In short: Makefile helps you automate the tedious compilation processes!

2. Why Use Makefile?

Suppose you have two source files:main.c and utils.c, the manual compilation steps are roughly as follows:

First, compile main.c and utils.c into object files:

gcc -c main.c -o main.o
gcc -c utils.c -o utils.o

2. Then link the object files into an executable file:

gcc main.o utils.o -o main

It looks simple, but as the code increases, the command becomes like this:

gcc -c file1.c -o file1.o
gcc -c file2.c -o file2.o
gcc -c file3.c -o file3.o
...
gcc file1.o file2.o file3.o -o my_program

Every extra command typed is another chance to make a mistake; if you change the code, you have to recompile everything, wasting time. With Makefile, you only need:

make

One command, and it’s all done! Plus, it will only compile the modified files, significantly improving efficiency.

Simply put:

No Makefile: manually typing commands is tiring.
With Makefile: just one command make, and everything else is done automatically, which is great.

3. Basic Structure of Makefile (Understand in One Minute)

Makefile consists of a set of rules, each rule contains three parts:

Target: the file you want to generate, such as main.
Dependencies: what source files or header files the target file needs.
Commands: the commands to run to generate the target.

For example:

main: main.o utils.o
 gcc main.o utils.o -o main

main.o: main.c
 gcc -c main.c

utils.o: utils.c
 gcc -c utils.c

What does this mean?

There are a total of 3 rules above, let’s discuss the first rule:

The target is main, indicating that we want to generate an executable file named main.
The dependencies are main.o and utils.o, meaning that to generate main, these two dependency files must be generated first, and these two dependencies are generated using rules 2 and 3.
The command is gcc main.o utils.o -o main, which is responsible for compiling the .o files into the final executable file.

The last two rules are similar, telling make how to generate main.o and utils.o.

Is it simple? This is equivalent to telling Makefile: “You need to prepare main.o and utils.o, and then use gcc to link them.”

4. Basic Functions of Makefile: Start Automating Compilation Here

4.1 Automatically Generate Object Files

If you manually write the generation rules for main.o and utils.o like above every time, Makefile will become very cumbersome and repetitive. The good news is that Makefile supports wildcards and can automatically generate rules!

%.o: %.c
 gcc -c $< -o $@

How to use this code? Suppose you have main.c and utils.c, Makefile will automatically generate the corresponding rules:

main.o: generated from main.c, command is gcc -c main.c -o main.o;
utils.o: generated from utils.c, command is gcc -c utils.c -o utils.o.

Explanation of symbols:

%.o and %.c: % is a wildcard, indicating file name matching, for example, main.o and main.c.
$: dependency file, for example, main.c.
$@: target file, for example, main.o.

With this rule, Makefile directly helps you generate all target files, isn’t that nice?

And as the number of project files increases, the advantages of using Makefile become even more significant.

4.2 Incremental Compilation: Only Compile Modified Files

Makefile has a fantastic feature:only compile the files that need to be updated. It checks the dependency files of each target, and if the dependency files have not changed, it skips the compilation.

For example, if you modify main.c, Makefile will only regenerate main.o, while utils.o remains unchanged. This feature can save a lot of time when there are many project files.

4.3 Clean Up Temporary Files

After compilation, many .o files and intermediate files will be left behind. Makefile can add a clean rule to help you clean up with one command:

clean:
 rm -f *.o main

Just run make clean, and it will be clean and tidy!

5. Advanced Uses of Makefile

After understanding the basic usage, let’s look at some advanced features that can improve development efficiency.

5.1 Basic Usage – Improve Readability and Maintainability

1. Use Variables: Make Makefile More Concise

How to use variables? For example, CC = gcc. Variables can make Makefile more flexible and easier to maintain.

Basic usage of variables:

# Define variables
CC = gcc
CFLAGS = -Wall -g
TARGET = main
SRCS = main.c utils.c
OBJS = $(SRCS:.c=.o) 

# $(SRCS:.c=.o) is a variable replacement in Makefile, which replaces each .c file name in the variable SRCS with the corresponding .o file name.
# After replacement, OBJS = main.o utils.o

When using variables in commands, you need to reference them in the form of $():

$(TARGET): $(OBJS)
 $(CC) $(CFLAGS) $(OBJS) -o $(TARGET)

# The rules after replacing variables with $() are as follows:
main: main.o utils.o
 gcc -Wall -g main.o utils.o -o main

In this way, if you want to change the compiler or optimization options, you only need to modify the variable part without manually changing each rule.

2. Phony Targets: Make Makefile More Flexible

In Makefile, some targets (like clean) do not generate files but are used to execute specific commands, such as cleaning up temporary files. These targets are called phony targets.

The problem arises: if there happens to be a file named clean in the directory, when running make clean, Makefile will mistakenly think that this file already exists, causing the rule not to execute.

How to solve it?

Use .PHONY to declare phony targets, telling make that this target is not a file and should directly execute the command.

Example: Declare a phony target

.PHONY: clean 
clean:
 rm -f $(OBJS) $(TARGET)

In this way, even if there is a file named clean in the directory, make clean will still execute according to the rules, deleting target files and intermediate files.

Remember: Any target that does not generate a file should be declared with .PHONY!

5.2 Advanced Usage – Build More Powerful Makefile

1. Pattern Rules: Adapt to More File Types

Sometimes our project contains not only .c files but also .cpp files. If we have to write rules separately, it would be too troublesome! At this time, pattern rules can be very helpful.

What are pattern rules?

Pattern rules are a type of generic rule used to tell Makefile:“When encountering this type of file, how to handle it.” For example, tell Makefile:

.c files are compiled with gcc;
.cpp files are compiled with g++.

In this way, Makefile will automatically select the correct rule based on the file extension, without you having to write them one by one.

How to use? Support C++ files

Suppose there are .cpp files in the project, we can add a pattern rule:

%.o: %.cpp
 g++ -c $< -o $@

In this way, Makefile will automatically compile all .cpp files into .o files, without you having to worry about it.

How to support both C and C++ files?

If the project contains both .c files and .cpp files, we can write two rules:

%.o: %.c
 $(CC) $(CFLAGS) -c $< -o $@

%.o: %.cpp
 g++ -c $< -o $@

The function of these two rules:

The first rule: tells Makefile that .c files are compiled with gcc.
The second rule: tells Makefile that .cpp files are compiled with g++.

In this way, whether your files are .c or .cpp, Makefile will automatically handle it.

To summarize:

It will automatically select the appropriate compilation method based on the file type;
You only need to write one rule, and Makefile can handle a large number of files;
No need to write rules repeatedly, saving time and improving efficiency!

Remember: Different file extensions? Use pattern rules to handle them all!

2. Conditional Statements: Make Makefile Smarter

Conditional statements can allow Makefile to adjust rules based on actual situations, such as different operating systems or different compilation modes, making it both flexible and worry-free.

1. Adapt to Different Platforms

The commands for different operating systems may vary, for example, deleting files, Linux uses rm, while Windows uses del. Through conditional statements, Makefile can automatically select the correct command:

OS = $(shell uname)

ifeq ($(OS), Linux)
 CLEAN_CMD = rm -f
else
 CLEAN_CMD = del
endif

clean:
 $(CLEAN_CMD) *.o $(TARGET)

Running on Linux with make clean: executes rm -f;
Running on Windows with make clean: executes del.

In this way, you don’t have to manually change commands on different platforms, which is convenient!

2. Switch Compilation Modes

During development, it is often necessary to switch between debug mode and release mode:

Debug mode: includes debugging information (helpful for troubleshooting).
Release mode: optimizes performance (suitable for production environments).

Using conditional statements makes it easy to implement:

ifeq ($(MODE), debug)
 CFLAGS = -g -O0
else
 CFLAGS = -O2
endif

all:
 $(CC) $(CFLAGS) -o $(TARGET) $(SRCS)

Run in debug mode:

make MODE=debug

Using -g and -O0 to compile, generating a program with debugging information.

Run in release mode:

make

or:

make MODE=release

Using -O2 to compile, generating an optimized high-performance program.

To summarize:

Adapt to different platforms: Conditional statements allow Makefile to work on both Linux and Windows.
Switch compilation modes: Convenient for debugging during development and optimizing for production environments.

3. Automated Dependency Management: Make Makefile Smarter!

When writing code, .c files often use header files .h. For example, your main.c may contain:

#include "utils.h"

If one day you modify utils.h, how does Makefile know it needs to recompile main.c?

Relying on you to manually write dependency rules? Don’t joke, with many project files, relying on manual dependency writing will exhaust you.

At this time, automated dependency management comes into play.

What is automated dependency management?

The core of automated dependency management is using gcc -M, which can help you automatically generate the dependency relationships between .c files and .h files. Every time you modify a header file, Makefile will automatically trigger the related .c files to recompile.

How to write the code?

See the following Makefile example:

# Define the list of dependency files
DEPS = $(SRCS:.c=.d)

# Generate .d files, write dependency rules
%.d: %.c
 $(CC) -M $< > $@

# Include dependency files
include $(DEPS)

What does it do?

Define dependency files

DEPS = $(SRCS:.c=.d)

Replace each .c file in the source file list SRCS with the corresponding .d file, for example:

main.c → main.d
utils.c → utils.d

These .d files are used to record the relationships between .c and .h files.

2. Automatically generate dependency rules

%.d: %.c
 $(CC) -M $< > $@

This rule will use gcc -M to generate a .d file for each .c file, which records what header files it depends on.

For example, if your main.c includes utils.h, the generated main.d file might look like this:

main.o: main.c utils.h

3. Include dependency rules

include $(DEPS)

This line tells Makefile to load the contents of all .d files. Every time Makefile runs, it will check the rules in the .d files to see which files need to be recompiled.

What is the effect?

Suppose you have the following files:

main.c depends on utils.h;
utils.c does not depend on any header files.

If you modify utils.h, Makefile will automatically discover this change and only recompile main.c, without touching utils.c.

The benefits of automated dependency management:

No more manual writing of dependency rules, making Makefile smarter;
Every time a header file is updated, Makefile automatically determines which files need to be recompiled;
Even if the project files are numerous, it can handle them easily.

Simply remember: “If there are .h files, use gcc -M to automatically generate dependencies!”

4. Multi-target Support: Use Makefile to Manage Multiple Modules

As your project files increase, even dividing into multiple modules, such as lib for core functionality and app for the main program module, relying on a single Makefile becomes very difficult.

At this time, the smart approach is:

Each module has its own Makefile, managing its own rules separately;
Use a master Makefile to schedule all modules, making the project clearer and more efficient!

Modular approach:

1. Write a separate Makefile for each module

For example, in the lib module directory, we write a lib/Makefile:

# lib/Makefile
lib.a: lib.o               # Define target lib.a
 ar rcs lib.a lib.o       # Package lib.o into static library lib.a

lib.o: lib.c               # Compilation rule: generate lib.o
 gcc -c lib.c -o lib.o

lib.a is a static library, ar rcs is the packaging command.
This Makefile only concerns the files in the lib module, without affecting other modules.

2. Use the master Makefile to schedule all modules

The master Makefile is located in the project root directory, responsible for stringing together all modules. It does not care about the specific rules of each module but recursively calls each module’s own Makefile:

# Master Makefile
SUBDIRS = lib app          # Define module directories

all: $(SUBDIRS)            # Master target: compile all modules

$(SUBDIRS):                # Recursively call each module's Makefile
 $(MAKE) -C $@

clean:                     # Clean all modules
 for dir in $(SUBDIRS); do $(MAKE) -C $$dir clean; done

Code explanation:

1. SUBDIR is the module list: Here it defines the modules in the project, such as lib and app. Each module directory has its own Makefile.

2. $(MAKE) -C $@ is key: This command means to switch to the specified directory (-C), and then run the Makefile in that directory. For example, $(MAKE) -C lib means to run its Makefile in the lib directory.

3. Recursive cleaning: The clean target will loop into each module directory and call their clean rules. Note that the double $$dir in $$dir is to allow Makefile to parse correctly.

Overall effect:

You can run make in the master directory, and it will automatically compile all modules;
When running make clean, it will recursively clean the temporary files of all modules;
Each module’s rules are independent, clear, and easy to maintain.

The benefits of using a master Makefile to schedule multiple modules:

Clear structure: Each module’s rules are managed independently, and the master Makefile only schedules.
Easy maintenance: When modifying or adding modules, just add the corresponding module directory in SUBDIRS.
Efficient recursion: By calling the subdirectory’s Makefile with $(MAKE) -C, modules do not interfere with each other.

In simple terms: manage by modules, schedule with the master Makefile, and everything is in order!

5.3 Advanced Techniques – Optimize Efficiency and Flexibility

1. Parallel Compilation: Improve Efficiency

The make command in Makefile supports parallel execution of multiple rules, using the -j parameter to specify the number of parallel tasks.

Example: Parallel Compilation

make -j4

This will run up to 4 tasks simultaneously, fully utilizing multi-core CPUs and significantly improving the compilation speed of large projects.

2. Custom Functions: Reuse Logic

When writing Makefile, if there is repeated compilation logic in the rules, such as compiling .c files into .o files, repeatedly writing $(CC) $(CFLAGS) is cumbersome. At this time, we can use custom functions to manage these repetitive operations uniformly, making it convenient and efficient!

Define a function:

Use define and endef to define a compilation function:

define compile
 $(CC) $(CFLAGS) -c $< -o $@
endef

compile is the function name, representing the compilation logic;
$ is the dependency file (like main.c), and $@ is the target file (like main.o).

Using the function:

When calling the custom function, use $(call function_name):

%.o: %.c
 $(call compile)

This rule will automatically compile .c files into the corresponding .o files.

To summarize:

Custom functions reduce repetitive code;
When modifying logic, you only need to change the function definition, and other places remain unchanged;
Makefile becomes concise and readable, clear and efficient.

In short: encapsulate repetitive logic into functions, and Makefile can also be elegant!

3. Static Pattern Rules: Batch Generate Target Files

When multiple files need to be compiled with similar rules, writing them one by one is too troublesome; using static pattern rules can solve it all at once!

First, let’s look at a simple example: Suppose we want to compile multiple .c files into .o files:

OBJS = main.o utils.o io.o

$(OBJS): %.o: %.c
 $(CC) $(CFLAGS) -c $< -o $@

What does this mean?

$(OBJS) is the target file list, such as main.o, utils.o;
%.o: %.c indicates that each .o file is generated from the corresponding .c file;
$ is the source file (like main.c), and $@ is the target file (like main.o).

The advantages:

Reduce repetition: one rule handles batch processing, saving time and effort;
Automatic matching: file names automatically correspond, no need to manually write each rule.

By the way, let’s mention pattern rules, these two types of patterns are similar in usage.

For simpler projects, you can use pattern rules to achieve similar effects:

%.o: %.c
 $(CC) $(CFLAGS) -c $< -o $@

Explanation:

Each .o file is generated from the corresponding .c file;
The wildcard % matches any file name, for example, main.c automatically corresponds to main.o.

Static Pattern Rules vs. Pattern Rules

Feature	Static Pattern Rules	Pattern Rules
Matching Scope	For specific target lists (like `<span>$(OBJS)</span>`)	Automatically matches all files that meet `<span>%</span>` criteria
Flexibility	More precise control, only processes specified target files	Simple and unified, suitable for global rules
Applicable Scenarios	Many files, complex rules, specific files need special handling	Few files, unified rules, simple projects

To summarize:

Pattern rules are suitable for simple projects, one rule handles all files;
Static pattern rules are suitable for complex projects, allowing precise control over which files apply the rules.

Remember: Use pattern rules for simple global handling, and static rules for precise processing!

4. Cross-Platform Builds: Use CMake to Generate Makefile

If the project needs to be compiled on multiple platforms (like Windows, Linux, macOS), writing Makefile directly can be cumbersome. At this time, you can use CMake to automatically generate Makefile that adapts to different platforms.

How to use:

1. Create a CMake Configuration File

Create a new CMakeLists.txt in the project directory, with the following content:

# Declare minimum version requirement
cmake_minimum_required(VERSION 3.10)
# Define project name
project(MyProject)
# Specify executable file
add_executable(main main.c utils.c)

2. Generate Makefile Run in the terminal:

cmake .

3. Compile the Project Use the generated Makefile:

make

Advantages:

Cross-platform: adapts to Windows, Linux, macOS, and other operating systems;
Simplified Management: no need to manually write complex Makefile.

In summary: Use CMake to automatically generate Makefile, cross-platform compilation is that simple!

6. Complete Example

Combining what we learned earlier, let’s look at a complete Makefile:

# Define variables
CC = gcc                     # Compiler
CFLAGS = -Wall -g            # Compilation parameters: enable all warnings and debugging information
SRCS =  $(wildcard *.c)      # Get all .c files in the current directory and assign them to the SRCS variable, for example: SRCS = main.c utils.c 
OBJS = $(SRCS:.c=.o)         # Replace .c files with .o files, after replacement, OBJS = main.o utils.o 
TARGET = main                # The final executable file to be generated

# Compilation rules
$(TARGET): $(OBJS)
 $(CC) $(CFLAGS) $(OBJS) -o $(TARGET)

# Generate .o file rules
%.o: %.c
 $(CC) $(CFLAGS) -c $< -o $@

# Add .PHONY to declare phony targets
.PHONY: clean

clean:
 rm -f $(OBJS) $(TARGET)

Usage:

make: generates the executable file main;
make clean: will delete all .o files and the executable file main, keeping the project directory clean.

After reading this article, I believe you should find the Makefile code above quite easy!

7. Final Thoughts: Start with Makefile, Move Towards Compilation Automation!

Makefile is the “lazy person’s tool” in compilation; once you use it, you will find:

No more manually typing commands, compilation becomes simpler;
Even as the project grows larger, managing it is effortless;
Improves efficiency, saves time, and easily handles complex compilations!

If you are still manually typing commands, hurry up and try writing a Makefile to experience the joy of automation!

In the next article, we will take you into the world of CMake, learning how to manage projects across platforms, stay tuned!

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Can Programmers Who Don't Understand Makefile Still Write Code?

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Can Programmers Who Don’t Understand Makefile Still Write Code?

Introduction: Tired of Typing Compilation Commands? It’s Time to Learn Automation!

1. What is Makefile?

2. Why Use Makefile?

3. Basic Structure of Makefile (Understand in One Minute)

4. Basic Functions of Makefile: Start Automating Compilation Here

4.1 Automatically Generate Object Files

4.2 Incremental Compilation: Only Compile Modified Files

4.3 Clean Up Temporary Files

5. Advanced Uses of Makefile

5.1 Basic Usage – Improve Readability and Maintainability

1. Use Variables: Make Makefile More Concise

2. Phony Targets: Make Makefile More Flexible

5.2 Advanced Usage – Build More Powerful Makefile

1. Pattern Rules: Adapt to More File Types

2. Conditional Statements: Make Makefile Smarter

3. Automated Dependency Management: Make Makefile Smarter!

4. Multi-target Support: Use Makefile to Manage Multiple Modules

5.3 Advanced Techniques – Optimize Efficiency and Flexibility

1. Parallel Compilation: Improve Efficiency

2. Custom Functions: Reuse Logic

3. Static Pattern Rules: Batch Generate Target Files

4. Cross-Platform Builds: Use CMake to Generate Makefile

6. Complete Example

7. Final Thoughts: Start with Makefile, Move Towards Compilation Automation!

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Introduction: Tired of Typing Compilation Commands? It’s Time to Learn Automation!

1. What is Makefile?

2. Why Use Makefile?

3. Basic Structure of Makefile (Understand in One Minute)

4. Basic Functions of Makefile: Start Automating Compilation Here

4.1 Automatically Generate Object Files

4.2 Incremental Compilation: Only Compile Modified Files

4.3 Clean Up Temporary Files

5. Advanced Uses of Makefile

5.1 Basic Usage – Improve Readability and Maintainability

1. Use Variables: Make Makefile More Concise

2. Phony Targets: Make Makefile More Flexible

5.2 Advanced Usage – Build More Powerful Makefile

1. Pattern Rules: Adapt to More File Types

2. Conditional Statements: Make Makefile Smarter

3. Automated Dependency Management: Make Makefile Smarter!

4. Multi-target Support: Use Makefile to Manage Multiple Modules

5.3 Advanced Techniques – Optimize Efficiency and Flexibility

1. Parallel Compilation: Improve Efficiency

2. Custom Functions: Reuse Logic

3. Static Pattern Rules: Batch Generate Target Files

4. Cross-Platform Builds: Use CMake to Generate Makefile

6. Complete Example

7. Final Thoughts: Start with Makefile, Move Towards Compilation Automation!

How to follow my public account?

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