Using Makefile to Depend on Other Makefiles in Linux

Hello everyone, I am the Intelligence Guy~

<span>$(MAKE) -C is very useful in building multiple packages, today I will detail its usage:</span>

<span><span>1. Usage of $(MAKE) -C</span></span>

<span>$(MAKE) -C</span> is a commonly used command combination in Makefile, which allows you to execute another Makefile in a specified directory. This is very useful when building complex or hierarchical projects.

Basic Syntax

$(MAKE) -C <directory> <target>

Where:

• <span>$(MAKE)</span>: References the Make command itself in the Makefile
• <span>-C <directory></span>: Switches to the specified directory to execute the Makefile
• <span><target></span>: The name of the target to execute (optional)

Simple Example

Assuming you have a project structure as follows:

project/
├── Makefile      # Top-level Makefile
└── src/
    └── Makefile  # Subdirectory Makefile

The top-level Makefile can call the Makefile in the src directory like this:

all: src

src:
    $(MAKE) -C src

clean:
    $(MAKE) -C src clean

When you execute <span>make</span> in the project root directory, it will automatically call the Makefile in the <span>src</span> directory. Executing <span>make clean</span> will call the <span>clean</span> target in the src directory.

Passing Variables

You can pass variables to the sub Makefile in the form of <span>VAR=value</span>:

all: src

src:
    $(MAKE) -C src CFLAGS="-O2"

clean:
    $(MAKE) -C src clean

Handling Errors

If you want the entire build process to fail when the sub Makefile fails, you can use <span>$(MAKE) -C <dir> <target> || exit 1</span>:

all: src

src:
    $(MAKE) -C src || exit 1

clean:
    $(MAKE) -C src clean || exit 1

2. A Relatively Complete Example

Here is a more complete example showing how to use <span>$(MAKE) -C</span> in a real project:

# Top-level Makefile

# Define some common variables
CC = gcc
CFLAGS = -Wall -g

# Define subdirectories
SUBDIRS = src lib utils

# Default target
all: $(SUBDIRS)

# Recursively build all subdirectories
$(SUBDIRS):
    $(MAKE) -C $@

# Clean target
clean:
    for dir in $(SUBDIRS); do \
        $(MAKE) -C $$dir clean; \
    done

# Install target
install:
    for dir in $(SUBDIRS); do \
        $(MAKE) -C $$dir install; \
    done

.PHONY: all $(SUBDIRS) clean install

Usage Tips

1. Avoid Circular Dependencies: Ensure your Makefile structure does not lead to circular dependencies, or it will get stuck in infinite recursion

2. Use <span>$(MAKE)</span> Instead of <span>make</span>: Always use <span>$(MAKE)</span> in the Makefile instead of directly using <span>make</span>, so that special options from the parent Makefile are preserved

3. <span>-k</span> Option: If you want to continue executing even if a sub Makefile fails, you can use <span>$(MAKE) -C <dir> -k</span>

4. Use <span>--no-print-directory</span>: If you do not want to display directory switching information every time you call a sub Makefile, you can add this option

I hope this guide helps you understand and use the <span>$(MAKE) -C</span> command to call other Makefiles.

END

Author:Mr.Deng

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