Interrupt Management and Configuration in FreeRTOS Development

1. Interrupt Priority

<span>Cortex-M</span> series cores (such as <span>M3/M4/M7</span>) use the <span>NVIC</span> (Nested Vectored Interrupt Controller) to support interrupt nesting and priority management. It employs a grouping mechanism that divides interrupt priority into two parts:

• Preemption Priority: Determines whether the current interrupt can interrupt other interrupts.
• Subpriority: Determines the response order when preemption priorities are the same.

Interrupt Priority Grouping

For <span>Cortex-M</span> series cores, the priority of each interrupt is set using 8 bits in a register, allowing for <span>2^8 = 256</span> levels of interrupts. However, not all of these levels are used, so chip manufacturers adjust the chips accordingly. (Taking the <span>4-bit</span> priority field as an example), the grouping is as follows:

Priority Group	Preemption Priority Bits	Subpriority Bits
NVIC_PriorityGroup_0	0	4	All used for subpriority
NVIC_PriorityGroup_1	1	3
NVIC_PriorityGroup_2	2	2
NVIC_PriorityGroup_3	3	1
NVIC_PriorityGroup_4	4	0	All used for preemption priority, recommended by FreeRTOS

Interrupt Nesting

• High preemption priority interrupts can interrupt low preemption priority interrupts.
• When interrupts with the same preemption priority arrive simultaneously, the interrupt with the higher subpriority is responded to first.
• Subpriority does not support interrupt nesting; if a low subpriority interrupt is executing, a high subpriority interrupt must wait until the low subpriority interrupt has finished executing before it can be responded to.
• <span>Reset</span>, <span>NMI</span>, and <span>Hard Fault</span> have higher priority than normal interrupts, and their priority cannot be configured.

Configuration Group

NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); ///< STM32
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); ///< AT32

2. Interrupt Mechanism

<span>FreeRTOS</span> imposes strict limitations on interrupts for safety and task scheduling correctness. Incorrect configuration may lead to <span>deadlocks</span> or <span>HardFault</span>.

Key Macro Definitions

In <span>FreeRTOSConfig.h</span>, the following definitions are present to configure interrupt-related settings:

• <span>configPRIO_BITS</span>: Indicates how many priority bits are actually used by <span>NVIC</span>, which depends on the chip platform and can be found in the chip manual.
• <span>configLIBRARY_LOWEST_INTERRUPT_PRIORITY</span>: The lowest interrupt priority (usually 0xF or 15, hardware-dependent, indicating that the interrupt cannot preempt any other).
• <span>configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY</span>: The highest interrupt priority that can call <span>FreeRTOS API</span> (lower value means higher priority).

Configuring Interrupt Priority

• Only interrupts with a priority greater than or equal to <span>configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY</span> can call <span>FreeRTOS API</span> (e.g., xSemaphoreGiveFromISR()).

Key Mechanisms of FreeRTOS

<span>FreeRTOS</span> uses the <span>BASEPRI</span> register of <span>ARM Cortex-M</span> to implement <span>critical section protection</span> and <span>interrupt masking</span>:

• <span>BASEPRI</span> sets an “interrupt masking threshold”.
• All interrupts with a priority higher than this threshold (i.e., lower value) will not be masked and can interrupt the critical section of <span>FreeRTOS</span>.

If a high-priority interrupt that cannot be masked by BASEPRI calls a <span>FreeRTOS API</span>, it may interrupt the scheduling logic of <span>FreeRTOS</span> in a critical section, potentially corrupting the kernel state, leading to deadlocks, memory errors, or <span>HardFault</span>!

3. Interrupt Configuration

• <span>#define configPRIO_BITS __NVIC_PRIO_BITS</span>
• This macro is used to configure the number of bits actually used in the priority setting register.
• <span>#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0X0F</span>
• This macro defines the lowest priority interrupt level used by FreeRTOS. This interrupt level is mainly used for the <span>SysTick</span> interrupt and <span>PendSV</span> interrupt. In a 4-bit configuration, 0x0F (15) is the lowest priority level.
• <span>#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 0x03</span>
• This macro is important as it defines the highest priority interrupt managed by FreeRTOS. It allows users to call FreeRTOS APIs within this interrupt service routine. 0x03 indicates that users can call FreeRTOS API functions in interrupts with preemption priorities from 3 to 15, while interrupts with preemption priorities from 0 to 2 are not allowed to call.
• <span>#define configKERNEL_INTERRUPT_PRIORITY</span>
• This macro defines the value of the interrupt priority register.
• <span>#define configMAX_SYSCALL_INTERRUPT_PRIORITY</span>
• This macro’s value is assigned to the <span>basepri</span> register. After assigning this macro’s value to the <span>basepri</span> register, global interrupt control can be implemented. For example, if the macro definition <span>configLIBRARY_LOWEST_INTERRUPT_PRIORITY</span> is <span>0x01</span>, after a 4-bit offset, it becomes <span>0x10</span>, which is <span>16</span>. After calling FreeRTOS to disable interrupts, all interrupts with priority values greater than or equal to <span>16</span> will be disabled. Interrupts with priority values less than <span>16</span> will not be disabled, and assigning 0 to the <span>basepri</span> register will enable the disabled interrupts.

4. Critical Protection

<span>FreeRTOS</span> implements a critical section protection mechanism to prevent interruptions during critical operations (such as accessing shared variables, task scheduling, and memory management), thereby ensuring data consistency and system stability.

Critical Section

In a multitasking system, multiple tasks or interrupt service routines may simultaneously access certain shared resources (such as global variables, linked lists, etc.). If a task switch or interrupt occurs during access, it may lead to data corruption. Therefore, critical section protection is needed to prevent interruptions during critical operations.

Protection Methods

a. Task Level

• Usage Scenario
• Used when multiple tasks access shared variables without interruption.
• Implementation Method:
• Task-level critical sections are implemented by masking task switches.
• Characteristics
• Prevents task switching (scheduler suspended).
• Interrupts are still allowed to occur.
• Used for protecting critical resources between tasks.
• Nesting is allowed (internally using a counter to track).
• Interface

taskENTER_CRITICAL();
    // Critical section code
taskEXIT_CRITICAL();

b. Interrupt Safe

• Usage Scenario
• Involves interrupts accessing shared resources, requiring prevention of interruptions during critical operations.
• Implementation Method
• Interrupt-safe critical sections are implemented by masking interrupts of certain priorities.
• Characteristics:
• Essentially sets the <span>BASEPRI</span> to mask interrupts above a certain priority.
• The protection scope only affects interrupts that can call <span>FreeRTOS</span> APIs.
• Generally used in <span>ISR</span> or high-concurrency environments.
• Interface

UBaseType_t uxSavedState = taskENTER_CRITICAL_FROM_ISR();
// Critical code
taskEXIT_CRITICAL_FROM_ISR(uxSavedState);

Previous Recommendations

RECOMMEND

[1]. FreeRTOS Development: Core Mechanisms and Important Concepts

[2]. FreeRTOS Development: How to Port to a Project

[3]. FreeRTOS Development: In-Depth Understanding of Various Configurations

[4]. FreeRTOS Development: How to Create Tasks

I am Aike, an embedded software engineer.

Follow me for more embedded insights.

Remember to like, share, and click ‘view’!

Your encouragement is my greatest motivation to continue sharing!

See you next time.

Looking forward to your

sharing

likes

views

NEWS

WeChat ID｜aike_eureka

Baijiahao｜Master Embedded Systems