In ARM-based MCU subsystems, there are only 240 peripheral interrupts available. Therefore, for a large number of interrupts, a secondary lookup is necessary. The cost of this approach is that it cannot achieve timely system responses, as it requires time to read the status registers.This article introduces the method of compressing interrupt signals and the … Read more
1. Interrupt Priority <span>Cortex-M</span> series cores (such as <span>M3/M4/M7</span>) use the <span>NVIC</span> (Nested Vectored Interrupt Controller) to support interrupt nesting and priority management. It employs a grouping mechanism that divides interrupt priority into two parts: Preemption Priority: Determines whether the current interrupt can interrupt other interrupts. Subpriority: Determines the response order when preemption priorities are … Read more
Source | Mculover666 To develop “advanced” applications based on RTOS, many principles of the kernel must be mastered. This article will explain how the RTOS kernel manages interrupts? How should users write interrupt handler functions? And how can users set critical sections? 1. Review of Knowledge — Interrupts 1.1. Interrupt Mechanism The interrupt mechanism is … Read more