Critical Section

Interrupt Management and Configuration in FreeRTOS Development

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Interrupt Management and Configuration in FreeRTOS Development

1. Interrupt Priority <span>Cortex-M</span> series cores (such as <span>M3/M4/M7</span>) use the <span>NVIC</span> (Nested Vectored Interrupt Controller) to support interrupt nesting and priority management. It employs a grouping mechanism that divides interrupt priority into two parts: Preemption Priority: Determines whether the current interrupt can interrupt other interrupts. Subpriority: Determines the response order when preemption priorities are … Read more

FreeRTOS – Task Scheduling Mechanism

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FreeRTOS - Task Scheduling Mechanism

Tasks are the smallest units of execution competing for system resources. Multiple tasks with the same priority can share the same priority level. In FreeRTOS, if configUSE_TIME_SLICING is defined as 1, then multiple ready tasks with the same priority will share the processor in a time-slicing manner, where one time slice equals one tick. Task … Read more

Who Says ADC Can’t Burst: The Crit Build

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Who Says ADC Can't Burst: The Crit Build

In version 6.12, the enhancement of many AD items naturally led us to believe that ADC heroes would rise. However, if we break down these enhanced items — Infinity Edge and Bloodthirster both increased in attack power, and the Armor Penetration Bow also added attack power, which means that crit-based heroes have a greater chance … Read more

Three Implementations of Critical Section Protection in Cortex-M Bare Metal

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Three Implementations of Critical Section Protection in Cortex-M Bare Metal

Today, Pi Zi Heng will share with you the three implementations of critical section protection in Cortex-M bare metal. Those who have worked with embedded systems and RTOS are likely familiar with the function codes OS_ENTER_CRITICAL() and OS_EXIT_CRITICAL(). In RTOS, multi-tasking (process) handling often occurs, and in some situations, certain special operations (such as Flash … Read more

Implementing Critical Section Protection in Cortex-M Bare Metal

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Implementing Critical Section Protection in Cortex-M Bare Metal

Source | Pi Zi Heng Embedded Today, I will share with you three implementations of critical section protection in Cortex-M bare metal environments. Friends who have worked with embedded systems and RTOS are probably very familiar with the functionality codes OS_ENTER_CRITICAL() and OS_EXIT_CRITICAL(). In an RTOS, there are often multi-task (process) handling situations where certain … Read more