Author/Original:Wolong Association Group Member Diandian
I2C Timing Stretching Issue!
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In hardware design, it is inevitable to deal with various interfaces, commonly used ones such as I2C, UART, SPI, and Ethernet. Each type of interface has its own requirements in design, but even the simplest things have their unique aspects. Today, we will discuss the timing stretching of I2C. Please add WeChat shineware666
Searching online for information about I2C, almost every article and document will tell you that the I2C lines need to be pulled up in hardware, and there are no other special requirements. Then, as long as the software timing matches the diagram below, it can meet your application scenario. Originally, we thought so too.
Recently, we used a TI chip that selected I2C as the control chip for reading or writing user data. During debugging, we found that using the TI programmer was always successful, but when we switched to our main controller for control, there were issues reading the registers.
Initially, engineers suspected a hardware issue because this I2C program had been verified on another program and could normally control the slave device. So, they removed other I2C devices and kept only this chip for testing. The situation remained the same. We used a logic analyzer to capture the waveform and found that communication failed every other time, with the IO timing not corresponding.
Thus, it was determined to be a software logic issue. The software engineer verified another model of the TI chip and found that data reading and writing were normal. This problem fell into a deadlock. Original WeChat Public Account: Wolonghui IT Technology
The project engineer decided to revisit the chip documentation and discovered a point that had not been noticed by everyone: Clock Stretching. The specification describes it as follows:
After researching some information online, it translates to: When the slave is in sleep mode, the slave will pull down the SCL for a period of time. At this time, the master must determine whether SCL is high to continue transmitting data. Once the slave is ready, it will release control of SCL, and then communication can happily begin.
Later, we checked the settings of the main chip and found that there was also a configuration for clock stretching. After enabling this feature, the system could read and write the chip normally. So, the next time you encounter abnormal I2C communication, remember to check if this issue is causing it.
Original: Wolong Association Group Member Diandian
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