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Written by: Original Author: 卧龙会 点点
I2C Timing Extension Issue!
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In hardware design, it is inevitable to deal with various interfaces, commonly used ones such as I2C, UART, SPI, and Ethernet. Each type of interface has its own requirements in design, but even the simplest things have their unique aspects. Today we will discuss the timing extension of I2C.
Searching for information on I2C online, almost every article or document will tell you that the I2C line needs pull-up processing in hardware, and there are no specific requirements. The timing in software should match the diagram below to meet your application scenario. Initially, we thought so too.
Recently, we used a TI chip that selected I2C as the control chip to read or write user data. During debugging, we found that using the TI programmer, it was successful every time, but when we switched to our main control to do the control, reading the registers would cause issues.
First, the engineers suspected a hardware issue because the I2C program was verified on another program and could normally control the slave device. Therefore, we removed other I2C devices and only kept this chip for testing. The situation remained the same. We used a logic analyzer to capture the waveform and found that communication failed every other time, and the IO timing did not match. Thus, it was determined to be a software logic issue. The software engineer verified another model of the TI chip and found that data reading and writing were normal, and the problem fell into a deadlock.
The project engineer decided to review the chip documentation and discovered a point that had been overlooked: Clock Stretching. The specification describes it as follows:
Some online resources explain that when the slave is in sleep mode, it will pull SCL low for a period of time. At this moment, the master must check if SCL is high to continue transmitting data. Once the slave is ready, it will release control of SCL, and then communication can begin smoothly.
Later, we checked the settings of the main chip and found that there was a clock stretching configuration. After enabling this feature, the system could read and write to the chip normally. So next time you encounter abnormal I2C communication, remember to check if this issue is the cause.
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