Handmade 16-bit RISC Architecture CPU

This week’s project shared with everyone comes from hackaday.

From the creation log, this project started at the end of 2018 and has been updated intermittently until a couple of days ago.

An interesting project that took a long time.

The project was initiated after the author learned about MITx’s “Computation Structures” course and realized that making a CPU might not be that difficult.

After mastering basic knowledge of electronics and the concepts introduced in the course, the author began designing a RISC CPU based on NMOS logic.

The course introduces the Beta CPU – which has a load-store, 32-bit RISC architecture.

To save space and transistors, and to lose a bit of hair, the author decided to reduce his CPU to 16 bits.

Note: The description of the MITx “Computation Structures” course on its official website is This course introduces architecture of digital systems, emphasizing structural principles common to a wide range of technologies.

This is equivalent to the courses on digital circuits and computer organization principles in our country.

There is a content creator on Bilibili who has done a translation; if interested, you can check it out: [MIT OpenCourseWare] 6.004 Computation Structures · Spring 2019 (Completed · Chinese and English Subtitles · Machine Translation)^[1]

Course original link: Computation Structures^[2]

If installed on the wall, it would take up an entire wall.

To make the entire computer look more retro, the author specifically took an old Apple II Plus from his closet to handle the input and output.

Note: The Apple II Plus was released in June 1979, which was 43 years ago…

The author constructed this CPU using a breadboard, prototype board, 2N7000 transistors, resistors (mainly SIP and some discrete components), LEDs, some HP-5082 display chips, some electroluminescent wires, and many cute colored jumpers.

The author named the entire computer – Spikeputer, with the goal of executing simple programs and visualizing the computation process.

Below is a description provided by the author:

Spikeputor will be a fully functional computer, with its CPU entirely made of NMOS logic, using about 5000 MOSFETs (2N7000), resistors, and LEDs to display logic.

HP-5082-7340 Hex display chips will be strategically added to show the numerical content output from the main CPU components, although if you read binary, the LEDs will provide the same information.

Electroluminescent wires will be used to visualize the logical paths between the main components.

The CPU’s clock frequency can be adjusted from the maximum speed (predicted to be in the tens of thousands of hertz range) down to single-step. (Note: GHz = gigahertz)

Since the main driving force behind making Spikeputor is to visualize the computation process, speed is not the most important factor, although steps will still be taken (like clock trees) to improve the overall performance of the computer.

Design Features and Main Components of Spikeputor CPU

• 16-bit address space
• Register memory: seven 16-bit registers, plus one hard-coded to 0.
• Multifunctional ALU
• Addition and subtraction, supporting negative two’s complement
• Comparison (equal, less than, less than or equal)
• Boolean logic (AND, OR, XOR, Identity)
• Shift operations
• Control logic implemented with simple logic gates (no microcode or ROM)
• Additional registers for program counter, instruction, constants, CPU stages, and some necessary status flags
• Single-byte opcode for operations between registers
• Double-byte opcode for operations between registers and 16-bit constants
• ALU functions (see above)
• Memory functions: load, load relative to PC, and store
• Conditional (BEQ, BNE) and unconditional branches, with branch point storage
• IRQ and RESET handling (including automatically using register R6 as an exception pointer)
• Direct memory access (DMA) for all I/O.

Memory

To execute more trivial programs, the Spikeputor CPU will connect with high-speed static RAM (2 x 32K AS6C62256) and ROM (2 x 32K AT27C256R) chips. Additionally, a mirrored write-only “screen memory” will be created, also made up of approximately 5000 transistors, providing a 48 by 18 addressable LED array. Memory addresses will be limited to word boundaries. Attempting to address odd memory locations will return the corresponding even 16-bit word. Due to the unavailability of any 16K SRAM and ROM chips, I used 32K chips and will design a memory system to select a 16K library for read operations from RAM and ROM. A complete 32K word (64kbytes) of RAM can be written to at any time.

I/O

The I/O functions are implemented using custom software and hardware running on the 1986 Apple II Plus computer. As part of the project, the author also designed a custom peripheral card named BIAS (the board connecting Apple and Spikeputor), along with software on the Apple to provide keyboard input, screen output, and long-term data storage and retrieval. The I/O controller will directly access Spikeputor memory and halt Spikeputor CPU during all read and write operations.

16-bit general input and output signals have also been implemented, mirrored to fixed high memory locations.

Structure

The entire Spikeputor is assembled on a series of solderless breadboards. Each main component (ALU, register memory, control logic/program counter/status register, and screen memory) is laid out on a 10.16cm × 5.08cm breadboard. Each breadboard can contain a 9×6 array (54) of breadboards and leave some space for small circuits as needed. Each of the four boards is mounted on the wall, with space below for the Apple II Plus table.

Power Supply

The power requirement is around 25W. Spikeputor uses a +5V power supply provided by a set of 8-port USB power supplies (one for each board), which is very convenient. The power for the electroluminescent wires is separate (an additional 5W).

Enjoy the pictures and videos:

A simple game:

Fibonacci sequence calculation:

Calculating pi:

References