Current Status of SiFive: How to Implement RISC-V?

I have a black leather notebook that I’ve been using since 2001, with the National Semiconductor logo on its cover. It holds sentimental value for me. Firstly, it reminds me of the breakfast I had with attendees at a National Semiconductor executive event in Laguna Niguel, California, on September 11, 2001. That morning, we were supposed to play golf, but we learned about the 9/11 tragedy while watching CNN. This notebook also reminds me of my promotion work for Philips Semiconductor’s TriMedia, which is a core processor with a very long instruction word produced by Philips. The UK chip manufacturer ARM saw its shipments increase nearly tenfold between 2004 and 2015. By 2001, InfoWorld awarded Red Hat Linux 6.1 the fourth “Operating System Product of the Year” award, indicating that open source was making significant strides in the operating system market. Now, people are particularly interested in the use of the open-source core RISC-V.

It turns out that there is not much difference in what is included when delivering proprietary soft IP cores versus open-source cores. You want a reliable company to provide a fully tested core. You need good documentation and a rich ecosystem. Data file formats should adhere to well-known industry standards. However, when considering RISC-V, it’s important to note that RISC-V is indeed open-source, but it is also scalable. What features do you want to include? This is a crucial factor in choosing a vendor.

Years ago, when Naveed Sherwani was the CEO of SiFive, we had a phone conversation. We discussed SiFive’s direction at that time. Since then, I haven’t had the chance to speak with him again, but I know SiFive has been making progress. Browsing the SiFive website, I found that they now offer many different standard IP cores, as well as development versions and software. The documentation page lists dozens of core manuals. To make designs as efficient as possible, SiFive can also provide further customized cores.

SiFive’s core designer customization tool is impressive. Through SiFive’s cloud interface, you can choose between 32-bit or 64-bit operating systems. You can continue to customize the core you choose with unique features required by your applications – this is why they are called “application-specific processors” (ASP). You can select different modes, the desired pipeline level, various instruction set architecture (ISA) extensions available, the number and arrangement of on-chip memory, various port configurations (e.g., AHB, JTAG, etc.), security features, debugging options, interrupts, and power management options. There is a considerable amount of customization possible. The speed at which SiFive builds its IP portfolio is indeed impressive.

SiFive is expected to release Chip Designer soon. SiFive claims this will be a new way to build custom chips. During the design steps, you can choose a template that fits your application. Currently, templates are available for implementations ranging from 28nm to 180nm. You can use the IP library from SiFive’s DesignShare partners or create design variants using your own IP. Then, prototyping will allow you to run application code and make changes to the design until you are satisfied with the performance. After that, you place an order, and SiFive will deliver sample chips within a few weeks. This is an interesting approach. I’ve only heard of similar methods before, and I can’t wait to hear the specific details SiFive plans to offer.

SiFive has indeed achieved a certain level of success in a short amount of time. The development of core processor IP over the past 20 years has been astonishing. By providing cores, tools, prototyping, large systems, and more, SiFive seems to be advancing the custom RISC-V cores needed to support its dynamic server pages. I believe the next two years will see better and faster developments.

Original link:https://semiwiki.com/semiconductor-ip/sifive/272852-considering-sifive-what-should-i-get-to-implement-a-risc-v-core/