This article is sourced from the SiFive Blog, translated and reposted to convey more information related to RISC-V, copyright belongs to the original author.
There Is No Best, Only Better – SiFive’s Latest Core IP Product Line Released
We are very pleased to announce a comprehensive update to the SiFive RISC-V IP portfolio in the SiFive 21G1 version. This release brings significant upgrades and new features to SiFive Core IP. SiFive Core IP is the most widely used RISC-V IP portfolio in the industry, covering everything from the ultra-high-performance U7 series to the popular E2 series processors, which can enhance bit processing algorithm performance by 35%; code size is reduced by 25%.
Performance Optimization for IoT and AI Applications
To improve computational throughput, the SiFive Core IP has undergone several key enhancements in the 21G1 version, including ISA architecture and processor interface connections. The SiFive 2 and 7 series processors now support RISC-V’s “bit manipulation” extensions – RV32B along with Zba and Zbb extensions. This extension provides higher performance for bit processing algorithms, such as accelerating cryptographic hash algorithms by 35%.
Previously, SiFive processors supported double-precision and single-precision floating-point operations. The 21G1 version adds half-precision floating-point (FP16) support for more complex floating-point operations. Half-precision floating-point operations were added based on user demand, aimed at reducing memory space and floating-point operation power consumption, as well as applications in AI algorithm computations (which widely use FP16).
Flexibility in SoC Hardware and Software Integration
The latest version provides more flexibility and options for software programming and hardware connections, enhancing the implementation of SoC based on SiFive processors. Address mapping is now fully user-configurable, allowing SoC architects to control the address mapping of storage and other modules to meet the requirements of traditional code or specific applications.
The new Sv48 option enables 48-bit virtual addressing and 47-bit physical addressing for U5 and U7 series products (RV64 application processors). This greatly expands the addressing range, allowing SiFive cores to be easily integrated into large system designs that require a significant amount of memory.
In this version, the 7 series processors have added a new ultra-low latency, high-bandwidth port called the “Core Local Port.” This port provides a dedicated connection for each processor. High-performance, time-critical hardware blocks can connect directly to the processor to provide low-latency throughput and fully deterministic operations for time-critical computations. Correspondingly, SiFive processors now support the new RISC-V NMI specification for mission-critical applications.
Higher Performance, Less Code
The 21G1 version introduces new computational features and support for new data types, enabling high performance. However, the core needs of SiFive users include reducing code size, memory, and costs. Therefore, SiFive focuses on improving library and toolchain support. A brand new, significantly improved C library has been fully integrated into the toolchain and SDK, allowing designers to achieve optimal performance while reducing code size by up to 25% (compared to the previous 20G1 version).
The enhancements in this version raise the benchmark performance of the 7 series processors to 5.18 CoreMarks/MHz and 2.63 Dhrystone/MHz.
Enhanced Tracing, Debugging, and Security
SiFive Insight is the industry’s first pre-integrated tracing and debugging IP for RISC-V processors, providing faster chip startup, hardware-software integration, and application development. The existing hardware encryption acceleration component in SiFive processors (SiFive Shield) has been further enhanced by adding a public key accelerator (HCA-PKA).
Uniquely, SiFive Insight achieves compatibility with native Arm® CoreSight™. Through seamless integration with Arm® CoreSight™, developers can embed SiFive’s RISC-V cores into mixed ISA designs while retaining their existing development environments. SiFive Insight has broad support from leading software companies in the industry, such as Green Hills Software, IAR Systems, Lauterbach, SEGGER, and the free tools of SiFive Freedom Studio are also compatible with SiFive Insight.
In this release, various new features greatly enhance tracing capabilities. Types of tracing (historical or branch), the number of communication channels, and the size of the tracing buffer are all optional. Historical tracing messages (HTM) provide 5x compression capabilities, recommended for high-performance multi-core applications generating large amounts of tracing data.
SiFive’s Best Product Portfolio
The SiFive 21G1 version offers new advanced computing capabilities, including bit manipulation combinations, half-precision floating-point support, and up to 25% code size reduction. The SoC integration of hardware and software has also been optimized for more efficient computation, smaller size, and faster time to market.
By using SiFive’s latest version of Core IP, defining and adopting a high-performance, efficient, and secure RISC-V processor for your next application or real-time SoC has never been more appealing. Leveraging SiFive’s unique support for Arm CoreSight minimizes workflow interruptions and provides extensive tool ecosystem support for SiFive Insight’s advanced tracing and debugging, saving time and effort.
We are eager to collaborate with customers to leverage the faster, more efficient, and powerful new features of the latest generation of SiFive Core IP to create amazing new products for our customers.
(1) The 35% performance improvement in bit manipulation computational algorithms is based on engineering test results from running cryptographic hash algorithms (nettle-sha256) on SiFive’s U7 series (21G1) processor core.
(2) The updated tools and C library in version 21G1, along with the 25% reduction in code size, are compared to the same toolchain version in version 20G1. 25% is the best and largest code reduction amount.
(3) Half-precision floating-point support includes a wide range of applications, including AI algorithm computations.
Arm and CoreSight are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the United States and/or other countries.
