Content IntroductionAbstract:This article proposes a programmable logic element (PLE) based on Sense-Switch type pFLASH technology. By programming the Sense-Switch type pFLASH, it achieves all three-input lookup table (LUT3) functions, some LUT4 functions, latch functions, and D flip-flop (DFF) functions with enable and reset. Because the PLE uses a method called Combinational Operation Logic (COOL) to compute logical functions, it allows for the implementation of any logical circuit using any combination of logic and registers. This essential characteristic brings it close to the fine granularity of basic ASIC units, allowing ASIC-like cell-based mappers to leverage all its optimization potential. Measured results of the Sense-Switch type pFLASH and PLE circuits show that the “on-state” drive current of the Sense-Switch type pFLASH is approximately 245.52 μA, and the “off-state” leakage current is about 0.1 pA; the programmable functionality of the PLE works normally; the typical delay for the combinational logic operation AND3 is 0.69 ns, and the delay for the sequential logic DFF is 0.65 ns, both meeting the design technical specifications..Keywords:Field-Programmable Gate Array; Programmable Logic Element; Boolean Logic Operations; Lookup Table; Sense-Switch type pFLASH; Threshold VoltageAuthors:
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Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yue’er SHAN, Yuting XU Affiliation: China Electronics Technology Group Corporation No. 58 Research Institute, Wuxi, Jiangsu, 214035, China Citation Format:Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, et al., 2024. Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH. Frontiers of Information Technology & Electronic Engineering, 25(4):485-499. https://doi.org/10.1631/FITEE.2300454 |
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