Decoding the Domain Controller Design of Roewe RX5 NGP Intelligent Driving Version

Source: Automotive Electronics and Software | Cover Image Source: Internet | Author: Programmer Kevin | Editor: ADS Think Tank

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SAIC Roewe’s third generation RX5 is the first fuel vehicle in China equipped with NGP intelligent navigation auxiliary driving function. It was launched in early August 2022 with NGP intelligent driving function. Today, we will decode the design scheme of SAIC Roewe RX5 NGP intelligent driving version domain controller.

This Article Directory

1 Roewe RX5 Intelligent Driving Program Overview	2.3 Core IC Introduction
2 Roewe RX5 Intelligent Driving Domain Controller Scheme	2.3.1 SOC
2.1 System Architecture	2.3.2 MCU
2.1.1 System Block Diagram	2.3.3 Storage Chip
2.1.2 Core IC List	2.3.4 Ethernet/Switch
2.2 Hardware Structure	2.3.5 Serializer/Deserializer Chip
2.2.1 Appearance Structure	2.3.6 Power Related Chips
2.2.2 Interface Layout	3 Roewe RX5 Domain Controller Cost Estimation
2.2.3 PCB

PART.01

Roewe RX5 Intelligent Driving Program Overview

To enhance users’ experience of advanced intelligent auxiliary driving functions, SAIC Roewe has invested significant effort in the vehicle’s perception sensor scheme. The all-new third-generation Roewe RX5 NGP intelligent driving version adopts a multi-dimensional perception fusion scheme, equipped with 1 8-megapixel 120° front-view camera, 5 2-megapixel 100° surround-view cameras, 4 360° panoramic cameras, 3 millimeter-wave radars, 12 ultrasonic radars, and high-precision positioning modules, totaling 28 sensors, providing comprehensive coverage of the vehicle’s surrounding environment, enabling the vehicle to have a longer detection distance, a wider detection range, and more accurate identification of more objects.

To achieve multi-sensor fusion and more complex algorithms, the SAIC Roewe NGP intelligent driving version domain controller is provided by Hongjing Intelligent Driving. This intelligent driving domain controller uses 3 high-performance domestic AI chips from Horizon Journey 3, which utilize Horizon’s self-developed Bernoulli 2.0 BPU® architecture, achieving various intelligent driving algorithm modules such as environmental perception, map positioning, and fusion planning, enabling 360° surround vision perception coverage. Furthermore, this system supports efficient intelligent driving planning and decision-making algorithms, has deep learning capabilities, and provides iterative updates and other functions.

PART.02

Roewe RX5 Intelligent Driving Domain Controller Scheme

2.1

Domain Controller System

2.1.1 System Block Diagram

Intelligent Driving Domain Control System Block Diagram

2.1.2 Core IC List

Intelligent Driving Domain Control Composition Diagram

2.2

Hardware Structure

2.2.1 Appearance Structure

The SAIC Roewe RX5 NGP intelligent driving version domain controller is designed by Hongjing Intelligent Driving, with a metal machined shell that has many heat dissipation grooves. This domain controller adopts a natural heat dissipation method, applying thermal silicone grease on the surface of the main chip, and having the metal column extending from the interior of the metal shell come into direct contact, thereby dissipating heat through the metal column connected to the shell into the external environment. The heat dissipation grooves on the outer shell of the domain controller increase the contact area with the air, facilitating better heat dissipation of the domain controller.

Intelligent Driving Domain Controller Front View

Intelligent Driving Domain Controller Back View

2.2.2 Interface Layout

The terminal pins of this domain controller are distributed on the left and right sides of the domain controller; the right side mainly distributes power, IO, communication interfaces, GPS antennas, etc.; the left side mainly distributes the harness terminals for surround view, panoramic view, and front view.

Intelligent Driving Domain Controller Terminal Diagram 1

Intelligent Driving Domain Controller Terminal Diagram 2

2.2.3 PCB

Intelligent Driving Domain Controller PCB Front View

Intelligent Driving Domain Controller PCB Front View

Intelligent Driving Domain Controller PCB Front Marked Diagram

In the diagram, the numbers are as follows:1-Horizon J3, 2-Micron DDR4 2G, 3-Samsung eMMC 64G, 4-American Chip NOR flash, 5-Infineon AURIX TC397, 6-Ublox ZED F9K, 7-NXP Switch SJA1105Q, 8-Power Chip MC33PF 8100A0ES, 9-Power Chip Infineon 355584, 10-PHY Chip RTL9010AA, 12-Power Management Chip MPF5024AMMA0ES.

Intelligent Driving Domain Controller PCB Back Marked Diagram

In the diagram, the numbers are as follows:Maxim GMSL MAX96712, Texas Instruments FDLink UB953, Maxim GMSL MAX9296A.

2.3

Core IC Introduction

2.3.1 SOC Chip

SOC, or System on Chip, is a large integrated circuit that integrates multiple functional modules such as processor core, memory controller, and peripheral controller. In the autonomous driving domain controller, the SOC chip is responsible for processing sensor data, performing real-time image processing, and computing visual algorithms. Common SOC chip models include Nvidia Drive Orin, Intel’s Mobileye EyeQ series, Qualcomm’s Snapdragon Automotive Platform series, and Horizon Journey series.

This time, the SAIC Roewe RX5 uses 3 Horizon J3 chips.

2.3.1.1 Functions of 3 Horizon J3 Chips

Chip Number	Function
J3-A	Responsible for perception of front-view camera and GNSS module positioning and mapping functions.
J3-B	Responsible for perception of surround-view camera, rear-view camera, and parking planning functions.
J3-C	Responsible for four-way panoramic camera perception and driving planning functions.

2.3.1.2 Introduction to Horizon Journey 3 Chip

Horizon Journey 3 is the second-generation vehicle-mounted intelligent chip under Horizon; Journey 3 is based on Horizon’s self-developed BPU®️2.0 architecture and complies with AEC-Q100. Journey 3 not only supports deep learning-based image detection, classification, pixel-level segmentation, etc.; it also supports efficient encoding of H.264 and H.265 video formats, making it an ideal platform for implementing multi-channel complex computing tasks and multi-channel digital video recording, such as enabling advanced driver assistance (ADAS), automatic parking assistance (APA), and other functions.

2.3.1.3 Features of Horizon Journey 3

General Characteristics

• Manufactured using TSMC’s 16nm FFC process;
• Using FCBGA484 package, pin pitch of 0.65mm, chip size of 15mmx15mm;

• Complies with automotive AEC-Q100 Grade 2 standards (operating temperature: -40~105 degrees Celsius)

CPU Characteristics

• Uses 4 Arm Cortex A53 cores, with 32KB/32KB L1 I/D core 512KB Level 2 cache;
• Maximum operating frequency: 1.2GHz;

• Supports Dynamic Frequency Scaling (DFS);

BPU Characteristics

• Composed of BPU0 core and BPU1 dual-core Bernoulli architecture, computing power of 5TOPS;
• Maximum operating frequency: 950MHz;

• Supports Dynamic Frequency Scaling (DFS);

DDR Characteristics

• Supports x32 external DDR4/LPDDR4/LPDDR4X DRAM, with a maximum capacity of 4GB;

• The maximum speed supported by DDR4 can reach DDR4-3200 MT/s;

• The maximum speed supported by LPDDR4/LPDDR4X can reach 3200MT/s;

Network Interface Characteristics

• Supports one Gigabit network interface;
• External Ethernet PHY supports RMII and RGMII protocols;

• Supports Time-Sensitive Networking (TSN) and Audio-Video (AV) traffic;

Host Interface

• Uses BIF-SPI slave interface, AP SPI master device transmission rate can reach up to 66 MHz;

• Suitable for AP eMMC master transmission mode, can reach up to 8 lines using BIF-SD device interface HS200 mode (maximum 192MB/s). The application processor (AP) uses BIF-SPI and BIF-SD master interfaces to access J3’s DDR, SRAM, and module registers for data exchange and control;

• Supports USB3.0 host/device dual-role high-speed interface.

2.3.1.4 Horizon Journey 3 Toolchain

2.3.2 MCU Chip

MCU chips play an important role in autonomous driving domain controllers. MCU, or Microcontroller Unit, is a small computer that integrates processor core, memory, input/output interfaces, and other functions. In autonomous driving domain controllers, MCU chips are responsible for real-time computing, data acquisition, and control tasks. Common MCU chip models include NXP’s S32K series, Infineon’s AURIX TC3X7 series, and Renesas’ RH850 series. MCU chips can communicate with SOC chips via CAN bus, Ethernet, and SPI.

TC397 chip in this domain controller function: responsible for overall vehicle control and data interaction.

2.3.2.1 Introduction to Infineon AURIX TC397

TC397 belongs to the Infineon AURIX 2G series product, which has up to six cores with a high-performance architecture, with a clock frequency of up to 300MHz, achieving high-speed computing capability; in terms of storage, this series of products supports a maximum of 16MB Flash and has A/B switching function, which can conveniently realize Over-The-Air (OTA) software updates; in terms of functional safety, this series of MCUs can be equipped with up to 4 lock-step cores, complying with ISO 26262 functional safety D level; and also has a built-in hardware encryption module – HSM, which is very useful in the field of autonomous driving.

2.3.2.2 TC397 Features

• Core: 6 TriCore™ running at 300 MHz (with 4 lock-step cores providing 4000 DMIPS)
• Flash: 16 MB Flash/ECC protection
• RAM: Up to 6.9 MB SRAM/ECC protection
• PHY: 1 Gbit Ethernet
• Peripherals: 12xCAN FD, 2xFlexRay, 12xLINs, 4xQSP, 2xI²C, 25xSENT, 6xPSI, 2xHSSL, 4xMSC, 1x eMMC/SDIO
• LVDS: 8×400 Mbit/s LVDS radar interface
• SPU: 2x SPU (Signal Processing Unit) for radar signal processing
• Timers: Redundant and diverse timer modules (GTM, CCU6, GPT12)
• Encryption: EVITA complete HSM (ECC256 and SHA2)
• Package: BGA-292 package
• Functional Safety: Developed and documented according to ISO 26262/IEC61508, to support safety requirements up to ASIL-D/SIL3
• AUTOSAR: AUTOSAR 4.2 support
• Power Supply: Single voltage power supply 5 V or 3.3 V

• Temperature: 165°C junction temperature

2.3.3 Storage Chips

Common storage modules used in intelligent driving domain controllers include eMMC and DDR4; they play an important role in storing data in autonomous driving domain controllers. The eMMC chip serves as a flash storage device, responsible for storing the system’s operating system, algorithms, and data. The DDR4 chip is a high-speed memory chip responsible for caching and running algorithms. Common eMMC chip models include Samsung’s KLM and SK Hynix’s eMMC, while common DDR4 chip models include Micron’s Crucial and Kingston’s HyperX.

2.3.3.1 DDR4

Micron DDR4 2GB

Specific model: MT53E1G32D2FW-046

2.3.3.2 eMMC

Model: KLMCG4JETD-B041, Samsung eMMC 64G

2.3.3.3 NOR FLASH

American Chip IS25WP512M-RHLA3 512Mb

2.3.4 Ethernet/Switch Chips

2.3.4.1 SJA1105Q

2.3.4.1.1 SJA1105Q Introduction

SJA1105P/Q/R/S aims to provide a cost-optimized and flexible solution for automotive Ethernet switches. The SJA1105P/Q variants are function-enhanced versions of the SJA1105/T, which are plug-and-play alternatives. In the SJA1105R/S variants, one port provides SGMII functionality. These devices can be used in applications that require SGMII connection to the host processor or applications that require cascading multiple devices.

The SJA1105P/Q/R/S series of automotive gigabit Ethernet switches extends the functionality of the SJA1105/SJA1105T switches with improved safety-related features, expanded interface options, and ISO 26262 ASIL-A compliance.

The SJA1105P/Q/R/S is a 5-port automotive Ethernet switch that supports IEEE Audio Video Bridging (AVB) and Time-Sensitive Networking (TSN) standards. Each of the five ports can be individually configured to operate at 10/100/1000 Mbit/s. This feature provides flexibility to connect any fast/gigabit/optical PHY or MCU/MPU to any port. Examples of external PHYs are NXP Semiconductors’ (and) TJA1100 and TJA1102 IEEE 100BASE-T1 PHY.

All SJA1105P/Q/R/S variants provide new frame whitelisting/blacklisting, port accessibility, and address learning limit functions that improve the security of the switch by limiting data processing to known frames and data sources and preventing the forwarding of erroneous or malicious data.

The updated MII/RMII/RGMII interfaces provide extended IO voltage such as 1V8 and 3V3 RGMII. Additionally, the SGMII interface available on the /R and /S variants expands the connection options for the switch. The /P and /Q variants do not have SGMII ports and maintain 100% pin compatibility with the SJA1105/SJA1105T switches.

The SJA1105P/Q/R/S switch series is developed according to ISO 26262 standards. ASIL-A compliance reduces the design burden for safety-critical ECUs. Additional documentation, including safety manuals, can be provided upon request.

These switches are compatible with IEEE AVB standards. The /Q and /S variants support extended TSN features such as 802.1Qbv. NXP’s original AUTOSAR drivers and AVB SW stack are available for this series.

SJA1105 Block Diagram

Each port of SJA1105 can be independently configured for 10/100 Mbit/s MII/RMII or 10/100/1000Mbit/s RGMII operation. The SGMII port on the SJA1105R/S can be configured for 10/100/1000 Mbit/s operation. The SPI slave interface provides access to the device registers from the host processor.

SJA1105P/Q/R/S Ethernet Switch Connection to PHY and Host Processor System Diagram

2.3.4.2 Ethernet Chip RTL9010AA

2.3.4.2.1 RTL9010AA Introduction

RT9010 is a low-noise, low-loss product with power capabilities of up to 300mA and power-on reset function. Operating from 2.5V to 5.5V input, the output voltage range is from 1.2V to 3.6V.

RT9010 features 2% accuracy, extremely low dropout (240mV@300mA), and very low ground current. The shutdown current approaches zero, making it suitable for battery-powered devices. Other features include current limiting, over-temperature, and output short-circuit protection.

RT9010 has a short-circuit thermal foldback protection feature. When an output short circuit occurs (VOUT<0.4V), RT9010 reduces its OTP trip point from 165°C to 110°C, providing maximum safety for the end user.

2.3.4.2.2 RTL9010AA Features

• Wide operating voltage range: 2.5V to 5.5V

• Low-noise RF applications

• No noise bypass capacitor required

• Fast response in line/load transients

• TTL logic controlled shutdown input

• Low temperature coefficient

• 300mA LDO output

• High accuracy ±2%

• Short-circuit protection

• Over-temperature protection

• Current limit protection

• Short-circuit thermal foldback protection

• Small TSOT-23-6 package

• RoHS compliant, 100% lead-free

2.3.5 Serializer/Deserializer Chips

2.3.5.1 MAX96712

2.3.5.1.1 MAX96712 Introduction

MAX96712 deserializer converts GMSL2 or GMSL1 serial input to MIPI CSI-2 D-PHY or C-PHY format output. This device allows simultaneous transmission of bi-directional control channel data during video transmission. MAX96712 can accommodate up to four remote sensors using industry-standard coaxial cables or STP interconnects. Each GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the forward direction and operates at 187.5Mbps in the reverse direction. In GMSL1 mode, MAX96712 can pair with first-generation 3.12Gbps or 1.5Gbps GMSL1 serializers or operate with GMSL2 serializers at up to 3.12Gbps.

MAX96712 supports aggregation and replication of video data, allowing data streams from multiple remote sensors to be combined and routed to one or more available CSI-2 outputs. Data can also be routed so that multiple streams from a single GMSL input can be independently routed to different CSI-2 outputs. Alternatively, frame-level cascading can be used to synchronize and combine data from multiple sensors into a single CSI-2 stream within a composite superframe. The CSI-2 interface supports 2x 4-channel and 4x 2-channel configurations using C-PHY or D-PHY.

Various peripheral communication options are provided for flexible local register access and remote device programming. Three I2C/UART ports support redundant local and remote internal register access for parallel or tunneled remote peripheral communication. Additionally, two SPI ports are provided as tunnel interfaces to remote peripherals (GMSL2).

2.3.5.1.2 MAX96712 Features

• MIPI CSI-2 v1.3 output configurable to 2×4 channels, 1×4 lane + 2×2 lanes, or 4×2 lanes

• Optional D-PHY v1.2, 80Mbps to 2.5Gbps/channel or C-PHY v1.0, 182Mbps to 5.7Gbps/channel
• 16/32 channel virtual channel support (D/C-PHY)
• Flexible aggregation and routing of incoming data via CSI-2 VC or frame-level cascading
• Data can be copied and routed to any CSI port
• Supports RAW8/10/12/14/16/20, RGB565/666/888, YUV422 8/10 bit formats
• Dual pixel mode for improved transmission efficiency
• CSI-2 lane reallocation and polarity inversion
• MIPI/GMSL video PRBS generator and checker
• Checkerboard/color gradient pattern generator
• Raw CSI-2 PRBS generator

• Independently configurable all video paths and GMSL/CSI-2 ports

• Four GMSL inputs with independently configurable GMSL1/2 operation, link speed, and video format

• Mixed support for GMSL1/GMSL2 and 3G/6G
• Backward compatible with GMSL1 serializers
• GMSL1 forward link speed up to 3.12Gbps
• GMSL2 link speeds of 3Gbps or 6Gbps (forward) and 187.5Mbps (reverse)
• Supports precise synchronization of multiple serializer systems for large camera systems
• GMSL PRBS generator/checker for link testing
• Eye monitor for continuous diagnostics
• Adaptive equalization for up to 15 meters of coaxial cable with multiple inline connectors

• Compatible with 50Ω coaxial cables or 100Ω STP

• ASIL-B compliant (GMSL2)

• Video watermark insertion and detection

• 16-bit CRC protection for control channel data that retransmits upon error detection

• Optional 32-bit CRC protection for video line data

• ECC protection for video data memory

• CRC protection for CSI-2 data stream

• Concurrent control channels for device configuration and communication with remote peripherals

• 3 I2C/UART, 2 SPI, 17 GPIO

• Eight hardware selectable device addresses

• Programmable spread spectrum to reduce EMI
• 64-lead 9mm x 9mm TQFN with exposed pads

MAX96712 System Diagram with Four Independent Inputs and Outputs

2.3.5.2 MAX9296A

MAX9296A deserializer converts single or dual serial inputs to MIPI CSI-2 output. This device operates in GMSL1 or GMSL2 mode. MAX9296A also transmits and receives side-channel data, achieving full-duplex transmission of forward path video and bi-directional control data, at a cost of 50Ω coaxial cables or 100Ω STP cables that comply with GMSL2 or GMSL1 channel specifications.

MAX9296A Physical Diagram

MAX9296A Two Independently Operating Video Source Block Diagram

2.3.5.3 UB953

2.3.5.3.1 UB953 Introduction

DS90UB953-Q1 serializer belongs to the TI FPD-Link III device series, designed to support high-speed raw data sensors, including 2.3MP/60fps imagers and 4MP/30fps cameras, satellite radar, lidar, and time-of-flight (ToF) sensors. This chip provides 4.16Gbps forward channel and ultra-low latency 50Mbps bi-directional control channel, and supports power over coaxial (PoC) or STP cables.

2.3.5.3.2 UB953 Features

• Complies with AEC-Q100 standard for automotive applications: – Device temperature level 2: environmental operating temperature range of -40°C to +105°C;
• Complies with ISO 10605 and IEC 61000-4-2 ESD standards;
• Coaxial cable powered (PoC) compatible transceiver;
• 4.16Gbps grade serializer supports high-speed sensors, including Full HD 1080p 2.3MP 60fps and 4MP 30fps imagers;
• System interface compliant with D-PHY v1.2 and CSI-2 v1.3 standards – up to 4 data channels, with a rate of 832Mbps per channel – supports up to four virtual channels
• Precision multi-camera clock and synchronization
• Flexible programmable output clock generator
• Advanced data protection and diagnostics, including CRC data protection, sensor data integrity checks, I2C write protection, voltage and temperature measurements, programmable alarms, and line fault detection
• Supports single-ended coaxial or shielded twisted pair (STP) cables
• Ultra-low power consumption (0.28W typical)
• Provides functional safety – documentation to assist in ISO 26262 system design
• Wide temperature range: -40°C to 105°C

• Small 5mm × 5mm VQFN package and PoC solution size, suitable for compact camera module designs

2.3.6 Power Related Chips

2.3.6.1 MC33PF 8100A0ES

2.3.6.1.1 Introduction

The PF81/PF82 PMIC series is designed for high-performance processing applications such as entertainment control, in-vehicle information services, dashboards, automotive networks, ADAS, views, and sensor fusion.

Two versions are offered to meet different market needs:

• PF82 with functional safety, compliant with ISO 26262 standards, providing a powerful and flexible solution for ASIL-B (D) automotive applications.

• PF81 is the basic version of this product, with power management and digital control functions, without functional safety, suitable for systems that do not require compliance with ASIL-B specifications.

8100A0ES Block Diagram

2.3.6.2 355584

2.3.6.2.1 Introduction

TLF35584 is a multi-output system power supply suitable for safety-related applications, providing 5V-μC, transceivers, and sensors through an efficient and flexible front/back regulator concept over a wide input voltage range. Due to the wide switching frequency range, it can be optimized for efficiency and the use of small filter components. A dedicated reference regulator powers the ADC, providing a step independent of the μC load and can be used as a tracking source for two independent sensor power supplies. Flexible state machines, including timers, and backup regulators help users select applications from various options.

2.3.6.2.2 Features

2.3.6.3 MPF5024AMMA0ES

Power management chip MPF5024AMMA0ES

2.3.6.3.1 Introduction

PF5024 integrates multiple high-performance buck regulators. It can operate as a standalone point regulator IC or as a companion chip to a larger PMIC.

Built-in one-time programmable (OTP) memory stores critical startup configurations, significantly reducing the external components usually used to set output voltage and regulator sequences. Regulator parameters can be adjusted post-startup via high-speed I2C for flexibility across different system states.

PF5024 is a power management integrated circuit (PMIC) designed as a building block for main power management of NXP high-end multimedia application processors like i.MX8 and S32V series. It is also capable of providing power solutions for high-end i.MX6 series and several non-NXP processors.

2.3.6.3.2 Features

• Buck Regulators

• SW1 to SW4: 0.4 V to 1.8 V; 2500 mA

• Dynamic voltage scaling

• Configurable as multi-phase regulators

• VTT termination mode on SW2

• Programmable current limit

• Spread spectrum of switching frequency and manual tuning

• PGOOD output and monitor

• Global PGOOD output and PGOOD monitor

• Independent PGOOD output for each regulator

• Independent enable input for each regulator
• Clock synchronization via configurable input/output sync pins

• System Features

• PMIC fast startup

• Advanced state machine for seamless processor interface

• High-speed I2C interface support (up to 3.4 MHz)

• User-configurable standby and shutdown modes

• Programmable soft start sequence and power-off sequence

• Programmable regulator configuration

• OTP (One-Time Programmable) memory for device configuration

• Monitoring circuits compliant with ASIL B safety level

• Independent voltage monitoring with programmable fault protection

• Advanced thermal monitoring and protection

• External watchdog monitoring and programmable internal watchdog counter

• I2C CRC and write protection mechanism

• Analog built-in self-test (ABIST)

PART.03

Roewe RX5 Domain Controller Cost Estimation

BOOM cost is approximately 3000 yuan. (BOOM detailed estimate list is as follows)

Model	Price
Horizon J3 * 3	1000
TC397 * 1	150
Emmc *3	75
DDR4 *3	240
Flash *3	105
GNSS *1	750
Switch *1	90
Ethernet *1	18
Deserializer	85+40
Serializer	40
Power Supply	50+30+40

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