Disassembly Analysis of Roewe RX5 MAX Intelligent Driving Domain Controller

“Automotive Controller Disassembly” column will share disassembly analysis of intelligent automotive controllers, presenting the latest mass-produced controller reference designs and selection schemes to readers.

This article will decode the design scheme of SAIC Roewe RX5 MAX domain controller. The Tier1 of this scheme is the joint venture company of SAIC and TTTech, Chuangshi Intelligent Driving. The Roewe RX5 MAX is equipped with 3 millimeter-wave radars, 6 full HD cameras, and 12 ultrasonic radars, enabling approximately 20 intelligent assisted driving functions.

#01

Appearance Structure of Intelligent Driving Domain Controller

Front View of the Autonomous Driving Domain Controller Enclosure

Back View of the Autonomous Driving Domain Controller Enclosure

#02

Interfaces of Intelligent Driving Domain Controller

The above image shows the power, CAN, GPIO, and gigabit Ethernet terminal interface diagram of Chuangshi Intelligent Driving domain controller

The above image shows the camera and antenna terminal diagram of Chuangshi Intelligent Driving

#03

PCB of Intelligent Driving Domain Controller

Front View of PCB

Back View of PCB

#04

System Composition of Intelligent Driving Domain Controller

Chuangshi Intelligent Driving’s domain controller uses a Texas Instruments DRA829 as the main control SOC, responsible for carrying out algorithms for perception, planning, etc.; the storage chip consists of a Samsung EMMC chip and a DDR4 chip; the deserializer uses a Maxim MAX96718 and MAX96722; the Ethernet chip is NXP’s JA1101A; the power management chip is a Texas Instruments TPS6594, two Maxim MAX20087, and a Texas Instruments LM5143; the CAN bus driver chip is NXP’s TJA1043. The following will explain the characteristics and functions of each chip in detail..

4.1, SOC Chip

4.1.1, Introduction to DRA829

The DRV829 processor is based on the evolving Jacinto™ 7 architecture, aimed at ADAS and autonomous vehicle (AV) applications, built on TI’s extensive market knowledge accumulated over more than a decade in the ADAS processor market. In an architecture aimed at meeting functional safety standards, the unique combination of high-performance computing, deep learning engines, and dedicated accelerators for signal and image processing makes the DRA829 device highly suitable for various industrial applications such as robotics, machine vision, radar, etc. The DRA829 provides high-performance computing for traditional and deep learning algorithms with an industry-leading power/performance ratio, and has a high degree of system integration, enabling scalability and lower cost for advanced automotive platforms that support multiple sensor modes in centralized ECUs or standalone sensors. Key cores include next-generation DSPs with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, the latest Arm and GPU processors for general computing, integrated next-generation imaging subsystems (ISP), video codecs, Ethernet hubs, and isolated MCU islands, all protected by automotive-grade safety hardware accelerators.

4.1.2, Role of DRA829 in Domain Controller

①, Perception Processing: The DRA829 achieves real-time processing and fusion of multi-sensor data for target detection, target recognition, lane departure warning, pedestrian recognition, and other functions through integrated high-performance processors and digital signal processors (DSPs). It can process data from various sensors such as cameras, millimeter-wave radars, ultrasonic sensors, etc.

②, Data Transmission and Storage: The DRA829 has high-speed data transmission and storage capabilities, supporting multi-channel high-speed data interfaces such as Ethernet, USB, CAN, etc., for real-time reception and transmission of sensor data. In addition, TDA4 also supports high-capacity storage devices that can store large amounts of onboard data for offline analysis and post-processing.

③, Decision Making and Planning: The DRA829 is equipped with a high-performance AI processor that can perform real-time decision-making and planning. It can predict and analyze the environment through deep learning models, generating safe and efficient path planning and dynamic decision-making for the navigation and driving control of autonomous vehicles.

④, Safety Assurance: The DRA829 has multiple safety mechanisms, including hardware encryption, cellular communication security, and system integrity checks. It can ensure the secure transmission and storage of sensitive data, enhancing the safety performance of the autonomous driving system.

4.1.3, Features

Processor Cores:	• C7x floating-point vector DSP, performance up to 1.0GHz, 80GFLOPS, 256GOPS • Deep learning matrix multiplication accelerator (MMA), performance up to 8TOPS (8b) (frequency at 1.0GHz) • Visual processing accelerator (VPAC) with image signal processor (ISP) and multiple vision assist accelerators • Depth and motion processing accelerator (DMPAC) • Dual-core 64-bit Arm® Cortex®-A72 microprocessor subsystem, performance up to 2.0GHz – each dual-core Cortex®-A72 cluster has 1MB L2 shared cache – each Cortex®-A72 core has 32KB L1 data cache and 48KB L1 instruction cache • Six Arm® Cortex®-R5F MCUs, performance up to 1.0GHz – 16K instruction cache, 16K data cache, 64K L2 TCM – two Arm® Cortex®-R5F MCUs in the isolated MCU subsystem – four Arm® Cortex®-R5F MCUs in the general computing partition • Two C66x floating-point DSPs, performance up to 1.35GHz, 40GFLOPS, 160GOPS • 3D GPU PowerVR® Rogue 8XE GE8430, performance up to 750MHz, 96GFLOPS, 6Gpix/s
Memory Subsystem:：	• Up to 8MB on-chip L3 RAM (with ECC and coherence) – ECC error protection – Shared coherent cache – Supports internal DMA engines • External memory interface (EMIF) module (with ECC) – Supports LPDDR4 memory type – Supports speeds up to 3733MT/s – 32-bit data bus with inline ECC, data rate up to 14.9GB/s • General memory controller (GPMC) • 512KB on-chip SRAM in the main domain, protected by ECC
Functional Safety:	• Aimed at meeting functional safety standards (on some device models) – Developed for functional safety applications – Documentation helps to ensure ISO 26262 functional safety system design meets ASIL-D/SIL-3 requirements – System functions comply with ASIL-D/SIL-3 requirements – For MCU domains, hardware integrity complies with ASIL-D/SIL-3 requirements – For main domains, hardware integrity complies with ASIL-B/SIL-2 requirements – Safety-related certification • Planned ISO 26262 certification • AEC-Q100 compliant (device models ending in Q1)
High-Speed Serial Interfaces	• Integrated Ethernet switch support (total of 8 external ports) – Up to 8 2.5Gb SGMII – Up to 8 RMII (10/100) or RGMII (10/100/1000) – Up to 2 QSGMII • Up to four PCI-Express® (PCIe) 3rd generation controllers – Up to 2 channels per controller – 1st generation (2.5GT/s), 2nd generation (5.0GT/s) and 3rd generation (8.0GT/s) operation with auto-negotiation • 2 USB 3.0 dual-role device (DRD) subsystems – 2 enhanced SuperSpeed 1st generation ports – Each port supports Type-C switching – Each port can be independently configured as USB host, USB peripheral or USB DRD
Automotive Interfaces:	• 16 modular controller area network (MCAN) modules with full CAN-FD support • 2 CSI2.0 4L RX and 1 CSI2.0 4L TX – Each channel has 2.5Gbps RX throughput (total throughput of 20Gbps)
Display Subsystem:	• 1 eDP/DP interface with multi-display support (MST) – HDCP1.4/HDCP2.2 high-bandwidth digital content protection • 1 DSI TX (up to 2.5K) • Up to 2 DPIs
Audio Interfaces:	• 12 multi-channel audio serial port (MCASP) modules
Video Acceleration:	• Ultra HD, 1 (3840 × 2160p, 60fps) or 2 (3840 × 2160p, 30fps) H.264/H.265 decoding • Full HD, 4 (1920 × 1080p, 60fps) or 8 (1920 × 1080p, 30fps) H.264/H.265 decoding • Full HD, 1 (1920 × 1080p, 60fps) or up to 3 (1920 × 1080p, 30fps) H.264 encoding

Block Diagram

4.2, Storage Chips

4.2.1, LDDR4-K4FBE3D4HM

K4FBE3D4HM Introduction

Storage capacity: 32GB

Read/write speed: 4266 Mbps

Function:

①, LPDDR4 can provide fast storage access speeds and high bandwidth, which is necessary for autonomous driving systems to perceive and analyze environmental data around the vehicle in real-time, including images, radar data, etc. The high-speed read and write capabilities of LPDDR4 can accelerate data transmission speed between the storage and processor, thereby improving the system’s response speed and real-time performance.

②, LPDDR4 features low power consumption. Autonomous driving systems require stable operation for extended periods and typically operate in embedded environments, where heat dissipation and power consumption control are essential considerations. The low power design of LPDDR4 can reduce the energy consumption of the controller, extend battery life, and minimize heat dissipation issues, enhancing system stability and reliability.

③, LPDDR4 supports high-density storage and large-capacity memory, which is needed for autonomous driving systems to store and manage large amounts of map data, vehicle status data, historical control information, etc. The high-density storage capabilities of LPDDR4 can meet these needs while ensuring high-speed read and write performance.

Features

• Double data rate architecture; two data transfers per clock cycle • Bidirectional data strobe (DQS_t, DQS_c) sent/received with data used by the receiver when capturing data • Differential clock input (CK_t and CK_c) • Differential data strobe (DQS_t and DQS_c) • Command and address inputs on the positive CK edge; two edges of DQS reference data and data mask • Each mold consists of 2 channels • Each channel has 8 internal banks • DMI pin: normal write and read operation’s DBI (data bus inversion), DMI off is used for masking write data (DM) -DBI on masks write DQ 1’s count# • Burst length: 16, 32 (OTF) • Burst type: continuous • Read/write latency: see Table 64 LPDDR4 AC timing table • Auto-precharge option for each burst access • Configurable drive strength • Refresh and self-refresh modes • Partial array self-refresh and temperature-compensated self-refresh • Write leveling • CA calibration • Internal VREF and VREF training • FIFO-based write/read training • MPC (multi-purpose command) • LVSTL (low-voltage swing terminated logic) IO • VDD1/VDD2/VDDQ:1.8V/1.1V/1.1V • VSSQ terminal • No DLL: CK to DQS not synchronized • Edge-aligned data output, data input center-aligned write training • Refresh rate: 3.9us

4.2.2, eMMC KLM8G1GETF

KLM8G1GETF-B041 Introduction

Storage capacity: 64GB

Function:

①, This EMMC chip is one of the main media for storing firmware and operating systems of the controller. The firmware and operating systems of the main controller are burned into the EMMC chip to load from the chip at startup. This ensures system stability and consistency, enabling the controller to start quickly.

②, The EMMC chip is also responsible for storing and managing the operational code in the controller. Autonomous driving controllers need to process a large amount of data and complex algorithms, and the running programs have very high requirements for real-time performance. The EMMC chip provides fast data read and write speeds, effectively executing the operational code of the controller and ensuring its normal operation.

③, The EMMC chip is also used to store and manage data within the controller. Autonomous driving systems need to record and store various sensor data, map data, and other important information in real-time to support real-time decision-making and improve algorithms. The EMMC chip provides large-capacity storage space and high-speed data read and write capabilities, meeting the data storage requirements of autonomous driving controllers.

4.3, Serializer/Deserializer Chips

4.3.1, Maxim MAX96722

Introduction

The MAX96722 deserializer converts GMSL2 or GMSL1 serial inputs into MIPI CSI-2 D-PHY or C-PHY format outputs. This device allows simultaneous transmission of bidirectional control channel data while performing forward video transmission on each link. The MAX96722 can accommodate up to four remote sensors using industry-standard coaxial cables or STP interconnects. Each GMSL2 serial link operates at a fixed rate of 3Gbps in the forward direction and 187.5Mbps in the reverse direction. In GMSL1 mode, the MAX96722 can pair with first-generation 3.12Gbps or 1.5Gbps GMSL1 serializers, or operate with GMSL2 serializers in GMSL1 mode at up to 3.12Gbps.

MAX96722 supports the aggregation and replication of video data, allowing streams from multiple remote sensors to be combined and routed to one or more available CSI-2 outputs. Data can also be routed based on virtual channel IDs, allowing multiple streams from a single GMSL input to be routed independently to different CSI-2 outputs. Alternatively, frame-level cascading can be used to synchronize and combine data from multiple sensors into a single CSI-2 stream within a composite superframe. The CSI-2 interface supports 2×4 lane and 4×2 lane configurations using C-PHY or D-PHY.

Features

MIPI CSI-2 v1.3 output configurable as 2×4 lanes, 1×4 lane + 2×2 lanes, or 4×2 lanes	• Optional D-PHY v1.2, 80Mbps-2.5Gbps/Lane or C-PHY v1.0, 182Mbps-5.7Gbps-Lane • 16/32 channel virtual channel support (D/C-PHY) • Flexible aggregation and routing of incoming data via CSI-2 VC or frame-level cascading • Data can be duplicated and routed to any CSI port • Supports RAW8/10/12/16/20, RGB565/666/888, YUV422 8-/10-bit formats • Dual pixel mode to improve transmission efficiency • CSI-2 lane reassignment and polarity inversion • MIPI/GMSL video PRBS generator and checker • Checkerboard/color gradient pattern generator • Raw CSI-2 PRBS generator • Independently configurable all video paths and GMSL/CSI-2 ports
Independently configurable four GMSL inputs GMSL1/2 operation, link speeds, and video formats	• Mixed GMSL1/GMSL2 support • Backward compatible with GMSL1 serializers • GMSL1 forward link speeds up to 3.12Gbps • GMSL2 link speeds of 3Gbps (forward) and 187.5Mbps (reverse)
Compatible with ASIL-B (GMSL2)	• Video watermark insertion and detection • 16-bit CRC protection for control channel data • Retransmission upon error detection • Optional 32-bit CRC protection for video line data • ECC protection for video data memory • CRC protection for CSI-2 data streams
Concurrent control channels for device configuration and communication with remote peripherals	• 3 I2C/UART, 2 SPI, 17 GPIO • Eight hardware selectable device addresses
Programmable spread spectrum to reduce EMI
Line fault monitoring for GMSL links
64-lead 9 x 9mm TQFN with exposed pads

Block Diagram

4.3.2, Maxim MAX96718

Performance similar to MAX96722, detailed chip manual not found!

4.4, Ethernet/Switch Chip

TJA1101 Introduction

The TJA1101 is an Ethernet PHY compliant with the 100BASE-T1 standard, optimized for automotive use cases such as gateways, IP camera links, driver assistance systems, and backbone networks. This device provides 100Mbit/s transmission and reception capability over two unshielded twisted pairs, supporting cable lengths of at least 15m.

The TJA1101 is designed for automotive robustness and ISO 26262, ASIL A compliance while minimizing power consumption and system costs. Due to its compliance with ASIL-A standards, sufficient safety features have been implemented to ensure that ASIL requirements are met at the system level.

Features

Functional Overview	Features
General	• 100BASE-T1 PHY • MII and RMII compatible interfaces for the bus • Compact HVQFN 36-pin package (6×6 mm) for PCB space-constrained applications • ISO 26262, compliant with ASIL-A
Optimized for automotive use cases	• Transmitter optimized for capacitive coupling with unshielded twisted pairs • Adaptive receive equalizer optimized for automotive cable lengths of at least 15 meters • Enhanced integrated PAM-3 pulse shaping for low RF emissions • EMC optimized driver strength for MII and RMII • MDI pins are ESD protected to ±6 kV HBM and ±8 kV IEC61000-4-2 • MDI pins protect against transients in automotive environments • MDI pins do not require external filtering or ESD protection • Automotive-grade temperature range of -40°C to +125°C • AEC-Q100 qualified automotive product
Low Power Mode	• Dedicated PHY enable/disable input pin to minimize power consumption • Suppressed voltage regulator controlled output • Complies with open alliance wake-up concept (global wake-up support) – Robust remote wake-up detection via the bus – PHY-level wake-up forwarding • Complies with open alliance sleep concept • Local wake-up pin • Wake-up via SMI access
Diagnostic Functions	• Real-time monitoring of link stability and transmission data quality • Cable fault diagnosis (short and open circuits) • No-gap power undervoltage detection with fault-muting behavior • Internal, external, and remote loopback modes for diagnostics
Other	• Reverse MII mode for back-to-back connection of two PHYs • On-chip regulator providing 3.3 V single supply operation • Optional 1.8 V external supply for digital core • On-chip termination resistors for differential cable pairs • Supports up to 16 kB jumbo frames

Block Diagram

4.5, Power Management Chips

4.5.1, TPS6594

The TPS6594-Q1 features five buck converters and four LDOs, suitable for automotive safety-related applications.

Features

Features	Functions
Meets automotive application requirements with the following features compliant with AEC-Q100 standards	– Input power supply voltage range of the device is 3V to 5.5V – Device temperature grade 1: –40°C to +125°C operating temperature range – Device HBM classification level 2 – Device CDM classification level C4A
Complies with functional safety standards	– Developed for functional safety applications – Documentation helps to ensure ISO 26262 system design meets ASIL-D requirements – Documentation helps to ensure IEC 61508 system design meets SIL-3 requirements – System functions comply with ASIL-D requirements – Hardware integrity complies with ASIL-D requirements – Input power voltage monitoring and over-voltage protection – Under-voltage/over-voltage monitoring and over-current monitoring on all output power rails – Watchdog with optional trigger/Q&A mode – Two error signal monitoring (ESM) with optional level/PWM mode – Temperature monitoring with high-temperature warning and thermal shutdown functionality – Bit integrity (CRC) error detection for internal configuration registers and non-volatile memory (NVM)
Low Power Consumption	– 2μA typical shutdown current – Typical value of 7μA in standby mode – Typical value of 20μA in low-power standby mode
Five switch-mode power buck regulators:	– Output voltage range: 0.3V to 3.34V (voltage steps of 5mV, 10mV or 20mV) – Output current: one at 4A, three at 3.5A, and one at 2A – Flexible multiphase functionality for the four buck regulators: single rail output current up to 14A – Short circuit and over-current protection – Internal soft start to limit inrush current – Switching frequency of 2.2MHz/4.4MHz – Can be synchronized with external clock input
Three low-dropout (LDO) linear regulators with configurable bypass mode	– Output voltage range in linear regulator mode: 0.6V to 3.3V (voltage steps of 50mV) – Output voltage range in bypass mode: 1.7V to 3.3V – 500 mA output current, with short circuit and over-current protection
One low-noise low-dropout (LDO) linear regulator	– Output voltage range: 1.2V to 3.3V (voltage steps of 25mV) – 300mA output current, with short circuit and over-current protection
Configurable power sequencing control in non-volatile memory (NVM):	– Configurable power-up and power-down sequences between power states – Digital output signals can be included in the power sequence – Digital input signals can trigger power sequence transitions – Configurable safety-related error handling
• 32kHz crystal oscillator, buffered 32kHz clock output • Real-time clock (RTC) with alarm and periodic wake-up mechanisms • One SPI or two I2C control interfaces, with the second I2C interface dedicated to Q&A watchdog communication

Functional Block Diagram

4.5.2, MAX20087

MAX20087 Introduction

Dual/Quad channel camera power protector; the industry’s only ASIL-rated camera protector, providing diagnostics via I2C. Maxim offers four camera power diagnostic chips: MAX20086, MAX20087, MAX20088, MAX20089.

MAX20086–MAX20089 dual/quad camera power detection ICs provide up to 600mA load current for each of the four output channels. Each output is individually protected against battery short circuits, ground short circuits, and over-current situations. The IC operates on a 3V to 5.5V supply and a 3V to 15V camera supply. At 300mA, the voltage drop from input to output is only 110mV (typical).

The IC provides enable inputs and an I2C interface to read the diagnostic status of the device. An onboard ADC can read the current through each switch. Versions compliant with ASIL B and ASIL D support reading an additional seven diagnostic measurements via the ADC, ensuring high fault coverage.

MAX20086–MAX20089 include over-temperature shutdown and over-current limit on each output channel. All devices are designed for ambient operating temperatures of -40°C to +125°C.

Features

Features	Functions
Small solution size	Up to 4 600mA protected switches 3V to 15V input supply voltage 3V to 5.5V device operating supply 26V battery short circuit isolation Adjustable current limit (100mA to 600mA) Parallel multi-channel for higher currents Optional I2C address Small size (4mm × 4mm), 20-pin SWTQFN and WETQFN package
High precision	±8% current limit accuracy 0.5ms soft start time 0.25ms soft shutdown time 0.3µA shutdown current 110mV voltage drop @ 300mA
Designed for safety applications	ASIL B/D compliant Short circuit diagnostics VBAT/GND Output over-voltage/under-voltage diagnostics Input over-voltage/under-voltage diagnostics Read 8-bit current, output voltage, and power readings via I2C Automatic retry on fault
AEC-Q100 certified, operating temperature range of -40°C to +125°C

4.5.2, MAX20087

#05

Estimated Cost of the Scheme

Chip	Price
DRA829	700
Samsung eMMC5.1 KLM8G1GEUF	18
Samsung LPDDR4 K4FBE3D4HM	100
Maxim MAX96718F	100
Maxim MAX96722	110
NXP 100M PHY transceiver JA1101A	18*2
Texas Instruments TPS6594	80
Maxim MAX20087A	20*2
NXP TJA1043	15*4
Texas Instruments LM5143	50

The estimated hardware cost of this scheme is around 1500!

About this Column:

This column will continue to disassemble the latest controller schemes from both domestic and foreign sources, including but not limited to intelligent driving, cockpit, central computing, body domain control, chassis domain control, and power domain control.

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