Column Introduction
“Automotive Controller Disassembly” column will share disassembly analysis of intelligent automotive controllers, presenting the latest reference designs and selection schemes for mass-produced controllers for readers.
This article decodes the design scheme of SAIC Roewe RX5 MAX domain controller. The Tier1 of this scheme is the joint venture company of SAIC and TTTech, Chuangshi Intelligent Driving. Roewe RX5 MAX is equipped with 3 millimeter-wave radars, 6 full HD cameras, and 12 ultrasonic radars, enabling around 20 intelligent driving assistance functions.
Front View of the Self-Driving Domain Controller Shell
Back View of the Self-Driving Domain Controller Shell
The above image shows the power, CAN, GPIO, and Gigabit Ethernet terminal interface diagram of Chuangshi Intelligent Driving domain controller.
The above image shows the camera and antenna terminal diagram of Chuangshi Intelligent Driving.
PCB Front View
PCB Back View
Chuangshi Intelligent Driving’s domain controller uses one Texas Instruments DRA829 as the main control SOC, responsible for the implementation carrier of perception, planning, and other algorithms; the storage chip consists of one Samsung EMMC chip and one DDR4 chip; the serializer uses one Maxim MAX96718 and MAX96722; the Ethernet chip is NXP’s JA1101A; the power management chip includes one Texas Instruments TPS6594, two Maxim MAX20087, and one Texas Instruments LM5143; the CAN bus driver chip is NXP’s TJA1043. Below, we will explain the characteristics and functions of each chip in detail.
4.1, SOC Chip
4.1.1, Introduction to DRV829
The DRV829 processor is based on the evolving Jacinto™ 7 architecture, aimed at ADAS and autonomous driving vehicle (AV) applications, built on TI’s extensive market knowledge accumulated over more than a decade in the ADAS processor market. In an architecture aimed at meeting functional safety standards, the unique combination of high-performance computing, deep learning engines, and dedicated accelerators for signal and image processing makes the DRA829 device very suitable for various industrial applications such as robotics, machine vision, and radar. The DRA829 provides high-performance computing for traditional and deep learning algorithms with industry-leading power/performance ratios, and has a very high degree of system integration, enabling scalability and lower costs for advanced automotive platforms supporting multiple sensor modes in centralized ECUs or standalone sensors. Key cores include next-generation DSPs with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, the latest Arm and GPU processors for general-purpose computing, integrated next-generation imaging subsystems (ISP), video codecs, Ethernet hubs, and isolated MCU islands. All of these are protected by automotive-grade safety hardware accelerators.
4.1.2, Role of DRA829 in Domain Controller
①, Perception Processing: The DRA829 can achieve real-time processing and fusion of multi-sensor data through integrated high-performance processors and digital signal processors (DSP), for functions such as object detection, object recognition, lane departure warning, and pedestrian recognition. It can process data from various sensors, including cameras, millimeter-wave radars, and ultrasonic sensors.
②, Data Transmission and Storage: The DRA829 has high-speed data transmission and storage capabilities, supporting multi-channel high-speed data interfaces such as Ethernet, USB, and CAN for real-time reception and transmission of sensor data. Additionally, the TDA4 supports high-capacity storage devices that can store large amounts of onboard data for offline analysis and post-processing.
③, Decision Making and Planning: The DRA829 is equipped with high-performance AI processors for real-time decision making and planning. It can predict and analyze the environment through deep learning models to generate safe and efficient path planning and dynamic decisions for the navigation and driving control of autonomous vehicles.
④, Safety Assurance: The DRA829 has multiple safety mechanisms, including hardware encryption, cellular communication security, and system integrity checks. It can ensure the secure transmission and storage of sensitive data, enhancing the safety performance of autonomous driving systems.
4.1.3, Features
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Processor Cores: |
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Block Diagram
4.2, Storage Chips
4.2.1, LDDR4-K4FBE3D4HM
K4FBE3D4HM Introduction
Storage capacity: 32GB
Read/write speed: 4266 Mbps
Function:
①, LPDDR4 provides fast storage access speeds and high bandwidth, which autonomous driving systems need to perceive and analyze environmental data around the vehicle in real-time, including images, radar data, etc. The high-speed read/write capability of LPDDR4 can accelerate the transfer speed of data between the memory and the processor, thereby improving the system’s response speed and real-time performance.
②, LPDDR4 features low power consumption. Autonomous driving systems require stable operation for long periods, often in embedded environments where heat dissipation and power consumption control are essential considerations. The low power design of LPDDR4 can reduce the controller’s energy consumption, extend battery life, and mitigate heat dissipation issues, enhancing system stability and reliability.
③, LPDDR4 supports high-density storage and large-capacity memory. Autonomous driving systems need to store and manage a large amount of map data, vehicle status data, historical control information, etc. The high-density storage capability of LPDDR4 can meet these demands while ensuring high-speed read/write and processing performance.
Features
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• Double data rate architecture; two data transfers per clock cycle • Bidirectional data strobe (DQS_t, DQS_c), sent/received together with the data used when capturing data by the receiver • Differential clock inputs (CK_t and CK_c) • Differential data strobes (DQS_t and DQS_c) • Commands and addresses input on the positive CK edge; data and data mask referenced by the two edges of DQS • Each module consists of 2 channels • Each channel has 8 internal banks • DMI pin: normal write and read operations with DBI (data bus inversion), used for masking write data when DBI is off (DM) -DBI on when masking write count #DQ 1 • Burst length: 16, 32 (OTF) • Burst type: continuous • Read/write latency: refer to table 64 LPDDR4 AC timing table • Auto-precharge option for each burst access • Configurable drive strength • Refresh and self-refresh modes • Partial array self-refresh and temperature-compensated self-refresh • Write leveling • CA calibration • Internal VREF and VREF training • FIFO-based write/read training • MPC (Multi-Purpose Command) • LVSTL (Low Voltage Swing Termination Logic) IO • VDD1/VDD2/VDDQ: 1.8V/1.1V/1.1V • VSSQ terminal • No DLL: CK to DQS not synchronized • Edge-aligned data output, data input center-aligned write training • Refresh rate: 3.9us |
4.2.2, eMMC KLM8G1GETF
KLM8G1GETF-B041 Introduction
Storage capacity: 64GB
Function:
①, This eMMC chip is one of the main media for storing the firmware and operating system of the controller. The firmware and operating system of the main controller are burned into the eMMC chip to load from the chip during startup. This ensures system stability and consistency, allowing the controller to start quickly.
②, The eMMC chip is also responsible for storing and managing the running code in the controller. The autonomous driving controller needs to handle a large amount of data and complex algorithms, and the programs run have very high requirements for real-time performance. The eMMC chip provides fast data read and write speeds, effectively executing the running code of the controller and ensuring its normal operation.
③, The eMMC chip is also used to store and manage the data in the controller. Autonomous driving systems need to record and store various sensor data, map data, and other important data in real time to support real-time decision-making and improve algorithms. The eMMC chip provides large storage space and high-speed data read/write capabilities, meeting the data storage requirements of the autonomous driving controller.
4.3, Serializer/Deserializer Chips
4.3.1, Maxim MAX96722
Introduction
The MAX96722 deserializer converts GMSL2 or GMSL1 serial input into MIPI CSI-2 D-PHY or C-PHY format output. This device allows simultaneous transmission of bidirectional control channel data while performing forward video transmission for each link. The MAX96722 can accommodate up to four remote sensors using industry-standard coaxial cables or STP interconnects. Each GMSL2 serial link operates at a fixed rate of 3Gbps in the forward direction and 187.5Mbps in the reverse direction. In GMSL1 mode, the MAX96722 can be paired with first-generation 3.12Gbps or 1.5Gbps GMSL1 serializers, or operate in GMSL2 mode with GMSL1 serializers up to 3.12Gbps.
The MAX96722 supports aggregation and replication of video data, allowing streams from multiple remote sensors to be combined and routed to one or more available CSI-2 outputs. Data can also be routed based on virtual channel IDs, allowing multiple streams from a single GMSL input to be routed independently to different CSI-2 outputs. Alternatively, frame-level cascading can be used to synchronize and combine data from multiple sensors into a single CSI-2 stream within a composite superframe. The CSI-2 interface supports 2×4 lane and 4×2 lane configurations using C-PHY or D-PHY.
Features
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MIPI CSI-2 v1.3 output configurable to 2×4 lanes, 1×4 lane + 2×2 lanes, or 4×2 lanes |
• Optional D-PHY v1.2, 80Mbps-2.5Gbps/Lane or C-PHY v1.0, 182Mbps-5.7Gbps-Lane • 16/32 channel virtual channel support (D/C-PHY) • Flexible aggregation and routing of incoming data via CSI-2 VC or frame-level cascading • Data can be replicated and routed to any CSI port • Supports RAW8/10/12/16/20, RGB565/666/888, YUV422 8-/10-bit formats • Dual pixel mode for improved transmission efficiency • CSI-2 lane reallocation and polarity inversion • MIPI/GMSL video PRBS generator and checker • Checkerboard/color gradient pattern generator • Raw CSI-2 PRBS generator • Independently configurable all video paths and GMSL/CSI-2 ports |
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Independently configurable four GMSL inputs for GMSL1/2 operation, link speed, and video format |
• Mixed GMSL1/GMSL2 support • Backward compatible with GMSL1 serializers • GMSL1 forward link speed up to 3.12Gbps • 3Gbps GMSL2 link speed (forward) and 187.5Mbps (reverse) • Supports synchronous and simultaneous operation of asynchronous cameras • Achieves precise synchronization of multiple serializers for large camera systems • GMSL PRBS generator/checker for link testing • Eye monitor for continuous diagnostics • Adaptive equalization for coaxial cables up to 15 meters with multiple inline connectors • Compatible with 50Ω coaxial cables or 100Ω STP |
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Compatible with ASIL-B (GMSL2) |
• Video watermark insertion and detection • 16-bit CRC protection of control channel data Retransmission when errors are detected • Optional 32-bit CRC protection of video line data • ECC protection of video data memory • CRC protection of CSI-2 data stream |
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Concurrent control channels for device configuration and communication with remote peripherals |
• 3 I2C/UART, 2 SPI, 17 GPIO • Eight hardware selectable device addresses |
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Programmable spread spectrum to reduce EMI |
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Line fault monitoring for GMSL links |
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64-pin 9 x 9mm TQFN with exposed pads |
4.3.2, Maxim MAX96718
Similar performance to MAX96722, detailed chip manual not found!
4.4, Ethernet/Switch Chip
TJA1101 Introduction
The TJA1101 is an Ethernet PHY compliant with the 100BASE-T1 standard, optimized for automotive use cases such as gateways, IP camera links, driver assistance systems, and backbone networks. This device provides 100Mbit/s transmission and reception capabilities over two unshielded twisted pairs, supporting cable lengths of at least 15m.
The TJA1101 is designed for automotive robustness and ISO 26262, ASIL A compliance, while minimizing power consumption and system costs. Due to compliance with ASIL-A standards, sufficient safety features have been implemented to ensure that ASIL requirements are met at the system level.
Features
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Functional Overview |
Features |
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General |
• 100BASE-T1 PHY • MII and RMII compatible interfaces for buses • Compact HVQFN 36-pin package (6×6 mm) suitable for PCB space-constrained applications • ISO 26262, compliant with ASIL-A |
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Optimized for automotive use cases |
• Transmitter optimized for capacitive coupling with unshielded twisted pairs • Adaptive receive equalizer optimized for automotive cable lengths of at least 15 meters • Enhanced integrated PAM-3 pulse shaping for low RF emissions • EMC optimized output driver strength for MII and RMII • MDI pins with ESD protection up to ±6 kV HBM and ±8 kV IEC61000-4-2 • MDI pins prevent transients in automotive environments • MDI pins do not require external filtering or ESD protection • Automotive-grade temperature range of -40°C to +125°C • AEC-Q100 qualified automotive product |
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Low Power Mode |
• Dedicated PHY enable/disable input pin to minimize power consumption • Suppressed output controlled by voltage regulator • Compliance with open alliance wake-up concept (global wake-up support) – Strong remote wake-up detection via bus – PHY-level wake-up forwarding • Compliance with open alliance sleep concept • Local wake-up pin • Wake-up access via SMI |
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Diagnostic Functions |
• Real-time monitoring of link stability and transmission data quality • Cable fault diagnostics (short circuit and open circuit) • No-gap power under-voltage detection with fault mute behavior • Internal, external, and remote loopback modes for diagnostics |
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Others |
• Reverse MII mode for back-to-back connection of two PHYs • On-chip regulator providing 3.3 V single supply operation • Supports optional 1.8 V external power for digital core • On-chip termination resistors for differential cable pairs • Supports large frame sizes up to 16 kB |
Block Diagram
TJA1101’s block diagram is shown below. The 100BASE-T1 section contains the functional blocks specified in the 100BASE-T-1 standard, which make up the physical coding sublayer (PCS) and physical media attachment (PMA) layer of the transmission and reception signal path. The MII/RMII interface (including the serial management interface (SMI)) complies with IEEE802.3 clause 22.
Additional blocks are defined for mode control, register configuration, interrupt control, system configuration, reset control, local wake-up, remote wake-up, under-voltage detection, and configuration control.
Many power-related functional blocks are defined: an internal 1.8V regulator for the digital core, a very low power (VLP) supply for sleep mode, reset circuitry, power monitoring, and inhibit control.
The clock signal required for the PHY’s operation is generated in the PLL block, derived from an external crystal or oscillator input signal.
Pin bundling allows many default PHY settings (e.g., master or slave configuration) to be hardware-configured at power-up.
4.5, Power Management Chips
4.5.1, TPS6594
The TPS6594-Q1 features 5 buck converters and 4 LDOs suitable for automotive safety-related applications.
Features
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Features |
Functions |
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Meets automotive application requirements，with AEC-Q100 compliant features |
– Device input power voltage range of 3V to 5.5V – Device temperature grade1：–40°C to +125°C Environmental operating Temperature range – Device HBM classification level 2 – Device CDM classification level C4A |
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Complies with functional safety standards
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– Developed for functional safety applications – Helps ISO 26262 system designs comply with ASIL-D documentation – Helps IEC 61508 system designs comply with SIL-3 documentation – System functions meet ASIL-D – Hardware integrity meets ASIL-D – Input power voltage monitoring and over-voltage protection – Under-voltage/over-voltage monitoring and over-current monitoring on all output power rails – Watchdog with optional trigger/Q&A mode – Two error signal monitoring with optional level/PWM mode(ESM) – Temperature monitoring with high temperature warning and thermal shutdown features – Bit integrity (CRC) error detection for internal configuration registers and non-volatile memory |
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Low Power Consumption
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– 2μA typical shutdown current – Typical value of 7μA only in standby mode – Typical value of 20μA in low-power standby mode
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Five switch-mode power buck regulators:
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– Output voltage range: 0.3V to 3.34V（voltage step of 5mV、10mV or 20mV） – Output current：one of which is 4A，the other three are 3.5A， and one is 2A – Flexible multi-phase functionality for the four buck regulators：Single-track output current up to 14A – Short-circuit and over-current protection – Internal soft start limits inrush current – Switching frequency of 2.2MHz/4.4MHz – Can be synchronized with external clock input
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Three low-dropout (LDO) linear regulators with configurable bypass mode:
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– Output voltage range in linear regulator mode: 0.6V to 3.3V （voltage step of 50mV） – Bypass mode output voltage range:1.7V to 3.3V – 500 mA output current，with short-circuit and over-current protection |
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One low-noise low-dropout (LDO) linear regulator:
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– Output voltage range: 1.2V to 3.3V（voltage step of 25mV） – 300mA output current，with short-circuit and over-current protection |
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Configurable power sequencing control in non-volatile memory (NVM):
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– Configurable power-on and power-off sequences between power states – Digital output signals can be included in power sequences – Digital input signals can trigger power sequence transitions – Configurable safety-related error handling |
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• 32kHz crystal oscillator, buffered to output 32kHz clock output • Real-time clock (RTC) with alarm and periodic wake-up mechanism • One SPI or two I2C control interfaces，with the second I2Cinterface dedicated to Q&A watchdog communication |
Functional Block Diagram
4.5.2, MAX20087
MAX20087 Introduction
Dual/Four Channel Camera Power Protector; the industry’s only ASIL-grade camera protector, providing diagnostics via I2C. Maxim has a total of 4 camera power diagnostic chips: MAX20086, MAX20087, MAX20088, MAX20089.
MAX20086–MAX20089 dual/four camera power detector ICs provide up to 600mA load current for each of the four output channels. Each output is individually protected from battery short circuits, ground short circuits, and over-current situations. The IC operates with a power supply of 3V to 5.5V and camera power from 3V to 15V. At 300mA, the input-to-output voltage drop is only 110mV (typical).
The IC provides enable input and I2C interface to read the diagnostic status of the device. The onboard ADC can read the current through each switch. Versions compliant with ASIL B and ASIL D support reading an additional seven diagnostic measurements via ADC, ensuring high fault coverage.
MAX20086–MAX20089 each include over-temperature shutdown and over-current limit on each output channel. All devices are designed for an environmental temperature range of -40°C to +125°C.
Features
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Features |
Functions |
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Small solution size
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Up to 4 600mA protected switches 3V to 15V input power voltage 3V to 5.5V device operating power 26V battery short circuit isolation Configurable current limit value (100mA to 600mA) Parallel multi-channel for higher currents Optional I2C address Small size (4mm × 4mm), 20-pin SWTQFN and WETQFN packages |
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High accuracy
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±8% current limit accuracy 0.5ms soft start time 0.25ms soft shutdown time 0.3µA shutdown current 110mV voltage drop at 300mA |
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Designed for safety applications |
Compatible with ASIL B/D Short circuit diagnostics VBAT/GND Output over-voltage/under-voltage diagnostics Input over-voltage/under-voltage diagnostics Read 8-bit current, output voltage, and power supply readings via I2C Automatic retry on fault occurrence |
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AEC-Q100 certified, operating temperature range of -40°C to +125°C |
4.5.2, MAX20087
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Chip |
Price |
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DRA829 |
700 |
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Samsung eMMC5.1 KLM8G1GEUF |
18 |
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Samsung LPDDR4 K4FBE3D4HM |
100 |
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Maxim MAX96718F |
100 |
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Maxim MAX96722 |
110 |
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NXP 100M PHY transceiver JA1101A |
18*2 |
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Texas Instruments TPS6594 |
80 |
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Maxim MAX20087A |
20*2 |
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NXP TJA1043 |
15*4 |
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Texas Instruments LM5143 |
50 |
This column will continue to disassemble the latest controller schemes from home and abroad, including but not limited to intelligent driving, cockpit, central computing, body domain control, chassis domain control, and power domain control.
To continuously launch popular controller disassemblies, this column will adopt
crowdfunding
to purchase relevant domain controller samples. Friends participating in the crowdfunding can order the controllers they are interested in and receive more detailed disassembly reports.
If you are willing to participate in crowdfunding disassembly, please contact the editor: btigh
teast.
Upcoming includes:
Intelligent Driving Domain Controller
: Large
Jiangsu vehicle domain control, Yangwang U8 domain control, Li Auto L8 domain control
Cabin Domain Controller: Xiaomi SU7, Mercedes-Benz E300, Zeekr 007, Leapmotor Clover
END