To enhance user experience with advanced intelligent assisted driving functions, Roewe has put a lot of thought into the sensor solution for the entire vehicle. The new third-generation Roewe RX5 NGP intelligent driving version adopts a multi-dimensional perception fusion scheme, equipped with one 8-megapixel 120° front-view camera, five 2-megapixel 100° surround view cameras, four 360° surround cameras, three millimeter-wave radars, twelve ultrasonic radars, and a high-precision positioning module, totaling 28 sensors, covering the vehicle’s surrounding environment comprehensively, providing a longer detection distance, a wider detection range, and more accurate identification of more objects.
To achieve the fusion of multiple sensors and implement more complex algorithms, the Roewe NGP intelligent driving domain controller is provided by Hongjing Intelligent Driving. This intelligent driving domain controller uses three Horizon Journey 3 high-performance domestic AI chips, which utilize Horizon’s self-developed Bernoulli 2.0 BPU® architecture to achieve various intelligent driving algorithm modules such as environment perception, map positioning, and fusion planning, achieving 360° surround visual perception coverage. In addition, the system supports efficient intelligent driving planning and decision-making algorithms, has deep learning capabilities, and provides iterative update functions.
1. Appearance Structure of Intelligent Driving Domain Controller
The Roewe RX5 NGP intelligent driving version domain controller is designed by Hongjing Intelligent Driving, with a metal machined shell and many heat dissipation grooves on the surface. This domain controller adopts a natural heat dissipation method for heat treatment, applying thermal grease on the surface of the main chip to make direct contact with the metal pillars extending from the internal metal shell, thereby dissipating heat through the shell connected to the metal pillars. The heat dissipation grooves on the outer shell of the domain controller can increase the contact area with air, further facilitating the heat dissipation of the domain controller.
Front View of the Intelligent Driving Domain Controller Shell
Back View of the Intelligent Driving Domain Controller Shell
2. Interfaces of the Intelligent Driving Domain Controller
The wire-speed terminals of this domain controller are distributed on both sides; the right side mainly distributes power, IO, communication interfaces, GPS antennas, etc.; the left side mainly distributes the wiring terminals for surround view, side view, and front view.
Wire-Speed Terminal Diagram 1 of the Intelligent Driving Domain Controller
Wire-Speed Terminal Diagram 2 of the Intelligent Driving Domain Controller
3. PCB Board of the Intelligent Driving Domain Controller
Front View of the Autonomous Driving Domain Controller PCB
PCB Annotated Diagram of the Autonomous Driving Domain Controller
The numbers in the figure are as follows:1-Horizon J3, 2-Micron DDR4 2G, 3-Samsung eMMC 64G, 4-American Chip Nor flash, 5-Infineon AURIX TC397, 6-Ublox ZED F9K, 7-NXP Switch SJA1105Q,8-Power Chip MC33PF 8100A0ES, 9-Power Chip Infineon 355584, 10-PHY Chip RTL9010AA, 12-Power Management Chip MPF5024AMMA0ES.
Back View Annotated Diagram of the Autonomous Driving Domain Controller PCB
The numbers in the figure are as follows:Maxim GMSL MAX96712, Texas Instruments FDLink UB953, Maxim GMSL MAX9296A.
4. Domain Controller System
System Block Diagram of the Autonomous Driving Domain Controller
Composition Diagram of the Autonomous Driving Domain Controller
5. SOC Chip
SOC, or System on Chip, is a large integrated circuit that integrates multiple functional modules such as processor cores, memory controllers, and peripheral controllers. In the autonomous driving domain controller, the SOC chip is responsible for processing sensor data, performing real-time image processing, and executing computer vision algorithms. Common SOC chip models include NVIDIA Drive Orin, Intel’s Mobileye EyeQ series, Qualcomm’s Snapdragon Automotive Platform series, and Horizon Journey series.
This time, the Roewe RX5 uses three Horizon J3 chips.
5.1 Functions of Three Horizon J3 Chips
|
Chip Number |
Function |
|
J3-A |
Responsible for perception of front-view camera and GNSS module positioning and mapping functions. |
|
J3-B |
Responsible for perception of surround-view cameras, rear-view cameras, and parking planning functions. |
|
J3-C |
Responsible for perception of four surround-view cameras and driving planning functions. |
5.2 Introduction to Horizon Journey 3 Chip
The Horizon Journey 3 is the second-generation vehicle intelligent chip under Horizon; it is based on Horizon’s self-developed BPU®️2.0 architecture and complies with AEC-Q100. The Journey 3 not only supports deep learning-based image detection, classification, pixel-level segmentation, etc.; it also supports efficient encoding of H.264 and H.265 video formats, making it an ideal platform for implementing multi-channel complex computing tasks and multi-channel digital video recording, such as achieving advanced driver assistance (ADAS), automatic parking assistance (APA), and other functions.
5.3 Features of Horizon Journey 3
|
General Characteristics |
· Uses TSMC’s 16nm FFC manufacturing process; · Uses FCBGA484 packaging, pin spacing of 0.65mm, chip size of 15mmx15mm; · Complies with automotive AEC-Q100 Grade 2 standards (operating temperature: -40~105 degrees Celsius) |
|
CPU Characteristics |
· Uses 4 Arm Cortex A53 cores, with 32KB/32KB L1 I/D core and 512KB Level 2 cache; · Maximum operating frequency: 1.2GHz; · Supports Dynamic Frequency Scaling (DFS); |
|
BPU Characteristics |
· Composed of BPU0 core and BPU1 dual-core Bernoulli architecture, computing power of 5TOPS; · Maximum operating frequency: 950MHz; · Supports Dynamic Frequency Scaling (DFS); |
|
DDR Characteristics |
· Supports x32 external DDR4/LPDDR4/LPDDR4X DRAM, maximum support of 4GB capacity; · Supported DDR4 maximum speed can reach DDR4-3200 MT/s; · Supported LPDDR4/LPDDR4X maximum speed can reach 3200MT/s; |
|
Network Interface Characteristics |
· Supports one Gigabit network interface; · External Ethernet PHY supports RMII and RGMII protocols; · Supports Time-Sensitive Networking (TSN) and Audio Video (AV) traffic; |
|
Main Host Interface |
· Uses BIF-SPI slave interface, AP SPI master device transmission rate can reach up to 66 MHz; · Suitable for AP eMMC host transmission mode, can reach up to 8 lines using BIF-SD device interface HS200 mode (maximum 192MB/s). Application processors (AP) use BIF-SPI and BIF-SD master interfaces to access J3’s DDR, SRAM, and module registers for data exchange and control; · Supports USB3.0 host/device dual-role high-speed interface. |
5.4 Toolchain for Horizon Journey 3
6. Storage Chips
Common storage modules used in intelligent driving domain controllers include eMMC and DDR4; they play an important role in storing data in autonomous driving domain controllers. The eMMC chip, as a flash storage device, is responsible for storing the operating system, algorithms, and data of the system. The DDR4 chip is a high-speed memory chip responsible for caching and running algorithms. Common eMMC chip models include Samsung’s KLM and SK Hynix’s eMMC, and common DDR4 chip models include Micron’s Crucial and Kingston’s HyperX.
6.1 DDR4
Micron DDR4 2GB, specific model: MT53E1G32D2FW-046
6.2 eMMC
Model: KLMCG4JETD-B041, Samsung eMMC 64G
6.3 NOR FLASH
American Chip IS25WP512M-RHLA3 512Mb
7. MCU Chip
The MCU chip plays an important role in autonomous driving domain controllers. The MCU, or Microcontroller Unit, is a microcomputer that integrates processor cores, memory, input/output interfaces, and other functions. In autonomous driving domain controllers, the MCU chip is responsible for real-time computing, data acquisition, and control tasks. Common MCU chip models include NXP’s S32K series, Infineon’s AURIX TC3X7 series, and Renesas’s RH850 series. The MCU chip can communicate with the SOC chip via CAN bus, Ethernet, and SPI.
The TC397 chip in this domain controller is responsible for overall vehicle control and data interaction.
Introduction to Infineon AURIX TC397
The TC397 belongs to the Infineon AURIX 2G series products, which feature a high-performance architecture with up to six cores, with a maximum clock frequency of 300MHz, achieving high-speed computing capabilities; in terms of storage, this series supports a maximum of 16MB Flash and has A/B switching capabilities, allowing for convenient over-the-air software updates (SOTA); in terms of functional safety, this series of MCUs can be equipped with up to four lockstep cores, meeting ISO 26262 functional safety level D requirements; and it also has a built-in hardware encryption module – HSM, very useful in the field of autonomous driving.
TC397 Features
|
Features |
Core:6 TriCore™ running at 300 MHz (with 4 lockstep cores, providing 4000 DMIPS) Flash:16 MB Flash/ECC protection RAM:Up to 6.9 MB SRAM/ECC protection PHY:1 Gbit Ethernet Peripherals:12xCAN FD, 2xFlexRay, 12xLINs, 4xQSP, 2xI²C, 25xSENT, 6xPSI, 2xHSSL, 4xMSC, 1x eMMC/SDIO LVDS:8×400 Mbit/s LVDS radar interfaces SPU:2x SPU (Signal Processing Unit) for radar signal processing Timers:Redundant and diversified timer modules (GTM, CCU6, GPT12) Encryption:EVITA complete HSM (ECC256 and SHA2) Package:BGA-292 packaging Functional Safety:Developed and documented according to ISO 26262/IEC61508 to support safety requirements up to ASIL-D/SIL3 AUTOSAR:AUTOSAR 4.2 support Power Supply:Single voltage power supply 5 V or 3.3 V Temperature:165°C junction temperature |
8. Serializer/Deserializer Chips
8.1 MAX96712
Introduction to MAX96712
MAX96712 deserializer converts GMSL2 or GMSL1 serial input to MIPI CSI-2 D-PHY or C-PHY format output. This device allows each link to simultaneously transmit bidirectional control channel data while video transmission is ongoing. MAX96712 can accommodate up to four remote sensors using industry-standard coaxial or STP interconnects. Each GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the forward direction and at a fixed rate of 187.5Mbps in the reverse direction. In GMSL1 mode, MAX96712 can pair with first-generation 3.12Gbps or 1.5Gbps GMSL1 serializers or operate with GMSL2 serializers at up to 3.12Gbps.
MAX96712 supports aggregation and replication of video data, allowing data streams from multiple remote sensors to be combined and routed to one or more available CSI-2 outputs. Data can also be routed so that multiple streams from a single GMSL input can independently route to different CSI-2 outputs. Alternatively, frame-level cascading can be used to synchronize and combine data from multiple sensors into a single CSI-2 stream within a composite superframe. The CSI-2 interface supports 2×4 lane and 4×2 lane configurations using C-PHY or D-PHY.
Various peripheral communication options are provided for flexible local register access and remote device programming. Three I2C/UART ports support parallel or tunnel-style remote peripheral communication for redundant local and remote internal register access. Additionally, two SPI ports are provided as tunnel interfaces to remote peripherals (GMSL2).
Features of MAX96712
|
Features |
Details |
|
MIPI CSI-2 v1.3 output configurable as 2×4 lanes, 1×4 lane + 2×2 lanes, or 4×2 lanes
|
• Optional D-PHY v1.2, 80Mbps to 2.5Gbps/channel or C-PHY v1.0, 182Mbps to 5.7Gbps/channel • 16/32 channel virtual channel support (D/C-PHY) • Flexible aggregation and routing of incoming data via CSI-2 VC or frame-level cascading • Data can be copied and routed to any CSI port • Supports RAW8/10/12/14/16/20, RGB565/666/888, YUV422 8/10-bit formats • Dual pixel mode to improve transmission efficiency • CSI-2 lane reallocation and polarity inversion • MIPI/GMSL video PRBS generator and checker • Checkerboard/color gradient pattern generator • Raw CSI-2 PRBS generator • Independently configurable all video paths and GMSL/CSI-2 ports |
|
Four GMSL inputs with independently configurable GMSL1/2 operation, link speed, and video format
|
• Mixed support for GMSL1/GMSL2 and 3G/6G • Backward compatible with GMSL1 serializers • GMSL1 forward link speed up to 3.12Gbps • 3Gbps or 6Gbps GMSL2 link speed (forward) and 187.5Mbps (reverse) • Supports synchronous and simultaneous operation of asynchronous cameras • Enables precise synchronization of multiple serializers for large camera systems • GMSL PRBS generator/checker for link testing • Eye monitor for continuous diagnostics • Adaptive equalization for up to 15 meters of coaxial cable with multiple inline connectors • Compatible with 50Ω coaxial cables or 100Ω STP |
|
ASIL-B compatible (GMSL2)
|
• Video watermark insertion and detection • 16-bit CRC protection for control channel data with retransmission on error detection • Optional 32-bit CRC protection for video line data • ECC protection for video data memory • CRC protection for CSI-2 data streams |
|
Concurrent control channels for device configuration and communication with remote peripherals |
• 3 I2C/UART, 2 SPI, 17 GPIO • Eight hardware selectable device addresses |
|
Programmable spread spectrum to reduce EMI |
|
|
64-pin 9mm x 9mm TQFN with exposed pads |
System Diagram of MAX96712 with Four Independent Inputs and Outputs
8.2 MAX9296A
MAX9296A deserializer converts single or dual serial inputs to MIPI CSI-2 output. This device operates in GMSL1 or GMSL2 mode. MAX9296A also sends and receives side channel data, enabling full-duplex transmission of forward path video and bidirectional control data, suitable for 50Ω coaxial cables or 100Ω STP cables that meet GMSL2 or GMSL1 channel specifications.
MAX9296A Physical Diagram
Block Diagram of Two Independently Operating Video Sources of MAX9296A
8.3 UB953
Introduction to UB953
DS90UB953-Q1 serializer belongs to the TI FPD-Link III device series, designed to support high-speed raw data sensors, including 2.3MP/60fps imagers and 4MP/30fps cameras, satellite radar, lidar, and time-of-flight (ToF) sensors. This chip provides 4.16Gbps forward channels and ultra-low latency 50Mbps bidirectional control channels, supporting power over coaxial (PoC) or STP cables. DS90UB953-Q1 features advanced data protection and diagnostic capabilities, supporting ADAS and autonomous driving. When combined with a compatible deserializer, DS90UB953-Q1 can provide precise multi-camera sensor clocking and sensor synchronization.
Features of UB953
|
Features |
• Complies with AEC-Q100 standards for automotive applications: – Device temperature grade 2: environmental operating temperature range of -40°C to +105°C; • Complies with ISO 10605 and IEC 61000-4-2 ESD standards; • Coaxial cable powered (PoC) compatible transceiver; • 4.16Gbps level serializer supports high-speed sensors, including full HD 1080p 2.3MP 60fps and 4MP 30fps imagers; • System interface compliant with D-PHY v1.2 and CSI-2 v1.3 standards – up to 4 data channels, each channel rate of 832Mbps – supports up to four virtual channels • Precise multi-camera clocking and synchronization • Flexible programmable output clock generator • Advanced data protection and diagnostics, including CRC data protection, sensor data integrity checks, I2C write protection, voltage and temperature measurements, programmable alarms, and line fault detection • Supports single-ended coaxial or shielded twisted pair (STP) cables • Ultra-low latency bidirectional I2C and GPIO control channel supports ISP control from the ECU side • 1.8V single power supply • Low power consumption (0.28W typical) • Provides functional safety – documentation to assist in ISO 26262 system design • Compatible with DS90UB954-Q1, DS90UB964-Q1, DS90UB962-Q1, DS90UB936-Q1, DS90UB960-Q1, DS90UB934-Q1, and DS90UB914A-Q1 deserializers • Wide temperature range: -40°C to 105°C • Small 5mm × 5mm VQFN package and PoC solution size suitable for compact camera module designs |
|
Applications |
• Advanced Driver Assistance Systems (ADAS) – Surround View Systems (SVS) – Camera Monitoring Systems (CMS) – Front View Cameras (FC) – Driver Monitoring Systems (DMS) – Rear View Cameras (RVC) – Automotive satellite radar and lidar modules – Time-of-Flight (ToF) sensors • Security and surveillance cameras • Industrial and medical imaging |
Typical Applications of UB953
9. Ethernet/Switching Chips
9.1 SJA1105Q
Introduction
SJA1105P/Q/R/S is designed to provide a cost-optimized and flexible solution for automotive Ethernet switches. The SJA1105P/Q variants are functionally enhanced versions of SJA1105/T, plug-and-play replacements. In the SJA1105R/S variants, one port provides SGMII functionality. These devices can be used in applications requiring SGMII connections to host processors or applications requiring cascading multiple devices.
The SJA1105P/Q/R/S series of automotive gigabit Ethernet switches enhances the functionality of the SJA1105/SJA1105T switches with improved safety-related features, expanded interface options, and ISO 26262 ASIL-A compliance.
The SJA1105P/Q/R/S is a 5-port automotive Ethernet switch that supports IEEE audio video bridging (AVB) and time-sensitive networking (TSN) standards. Each of the five ports can be individually configured to operate at 10/100/1000 Mbit/s. This feature provides flexibility to connect any fast/gigabit/optical PHY or MCU/MPU to any port. Examples of external PHYs include NXP Semiconductor’s TJA1100 and TJA1102 IEEE 100BASE-T1 PHY.
All SJA1105P/Q/R/S variants provide new frame whitelist/blacklist, port reachability, and address learning limitation features, improving the switch’s security by limiting data processing to known frames and data sources, preventing erroneous or malicious data from being forwarded.
The updated MII/RMII/RGMII interfaces provide extended IO voltages such as 1V8 and 3V3 RGMII. Additionally, the SGMII interface available on the /R and /S variants expands the switch’s connection options. The /P and /Q variants do not have SGMII ports and maintain 100% pin compatibility with the SJA1105/SJA1105T switches.
The SJA1105P/Q/R/S switch series is developed according to the ISO 26262 standard. ASIL-A compliance reduces the design burden for safety-critical ECUs. Additional documentation, including safety manuals, is available upon request.
These switches are compatible with the IEEE AVB standard. The /Q and /S variants support extended TSN features such as 802.1Qbv. NXP’s original AUTOSAR drivers and AVB SW stack are available for this series.
SJA1105 Block Diagram
Each port of SJA1105 can be independently configured for 10/100 Mbit/s MII/RMII or 10/100/1000 Mbit/s RGMII operation. The SGMII port on SJA1105R/S can be configured for 10/100/1000 Mbit/s operation. The SPI slave interface provides access to device registers for the host processor.
System Diagram of SJA1105P/Q/R/S Ethernet Switch Connected to PHY and Host Processor
9.2 Ethernet Chip
RTL9010AA
Introduction
RT9010 is a low-noise, low-loss product with power capabilities of up to 300mA and power-on reset functionality. Operating from 2.5V to 5.5V input, the output voltage range is from 1.2V to 3.6V.
RT9010 features 2% accuracy, very low dropout (240mV@300mA), and very low ground current. The shutdown current is close to zero, making it suitable for battery-powered devices. Other features include current limiting, over-temperature, and output short-circuit protection.
RT9010 has short-circuit thermal foldback protection. When an output short circuit occurs (VOUT<0.4V), RT9010 will reduce its OTP trip point from 165°C to 110°C, providing maximum safety for the end user.
Features
|
Features |
|
10. Power Modules
Power management modules are also an important component in autonomous driving domain controllers. Power management chips are responsible for managing the power supply and energy management of the entire system, ensuring that each component operates normally.
10.1 MC33PF 8100A0ES
Introduction
The PF81/PF82 PMIC series is designed for high-performance processing applications, such as entertainment control, automotive information services, dashboards, automotive networks, ADAS, and sensor fusion.
Two versions are provided to meet different market needs:
-
PF82 with functional safety, compliant with ISO 26262 standards, providing a powerful and flexible solution for ASIL-B (D) automotive applications.
-
PF81 is the base version of this product, with power management and digital control functions, without functional safety, suitable for systems that do not require compliance with ASIL-B standards.
8100A0ES Block Diagram
Features
10.2 355584
① Introduction
TLF35584 is a multi-output system power supply suitable for safety-related applications, providing 5V-μC, transceivers, and sensors through efficient and flexible front/rear regulator concepts across a wide input voltage range. Due to the wide switching frequency range, efficiency and the use of small filter components can be optimized. Dedicated reference regulators power the ADC, providing independent steps from the μC load and can be used as tracking sources for two independent sensor power supplies. Flexible state machines, including timers and wake-up concepts, as well as backup regulators help users choose to use in various applications.
② Features
10.3 MPF5024AMMA0ES
The power management chip MPF5024AMMA0ES
Introduction
PF5024 integrates multiple high-performance buck regulators. It can operate as an independent point for load regulation ICs or as a supporting chip for larger PMICs.
Built-in one-time programmable (OTP) memory stores critical start-up configurations, significantly reducing the external components usually required to set output voltages and regulator sequences. Regulator parameters can be adjusted via high-speed I2C after startup to provide flexibility for different system states.
PF5024 is a power management integrated circuit (PMIC) designed for building blocks of main power management i.MX8 and S32V series NXP high-end multimedia application processors. It also provides power solutions for high-end i.MX6 series and several non-NXP processors.
Features
-
Buck Regulator
–SW1 to SW4: 0.4 V to 1.8 V; 2500mA
–Dynamic voltage scaling
–Configurable as multiphase regulators
–VTT termination mode on SW2
–Programmable current limit
–Spread spectrum and manual tuning of switching frequency
-
PGOOD output and monitor
–Global PGOOD output and PGOOD monitor
–Independent PGOOD output for each regulator
-
Independent enable input for each regulator
-
Clock synchronization through configurable input/output sync pins
-
System Functions
–PMIC fast startup
–Advanced state machine for seamless processor interface
–High-speed I2C interface support (up to 3.4 MHz)
–User-programmable standby and shutdown modes
–Programmable soft-start sequence and power-down sequence
–Programmable regulator configuration
-
OTP (One-Time Programmable) memory for device configuration
-
Monitoring circuits compliant with ASIL B safety levels
–Independent voltage monitoring with programmable fault protection
–Advanced thermal monitoring and protection
–External watchdog monitoring and programmable internal watchdog counter
–I2C CRC and write protection mechanisms
–Analog built-in self-test (ABIST)
It is understood that this power chip has been discontinued.
|
Model |
Price |
|
Horizon J3 * 3 |
1000 |
|
TC397 * 1 |
150 |
|
Emmc *3 |
75 |
|
DDR4 *3 |
240 |
|
Flash *3 |
105 |
|
GNSS *1 |
750 |
|
Switch *1 |
90 |
|
Ethernet *1 |
18 |
|
Serializer |
85+40 |
|
Deserializer |
40 |
|
Power Supply |
50+30+40 |
BOOM cost is about 3000 yuan.
Source: Automotive Electronics and Software
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