Scheme 1
Scheme 1: The clutter data is divided into 16 segments for storage. Upon receiving a pulse signal, a FIR filter is used to perform convolution, and the multiple segments of data are stored with delays for combined output..
Advantages: Fast speed; the first valid data can be output after 1/fs*16k time after receiving the signal, and all combined signals can be output within 1ms..
Disadvantages: The FIR architecture uses a lot of DSP resources and requires multiple FPGAs to work in parallel. Additionally, it involves complex convolution, necessitating a fourfold increase in the resources mentioned above.
Scheme 2
Scheme 2: The clutter data is divided into 16 segments, and 32K is supplemented on the host computer to perform FFT. The generated data is stored in ROM. Upon receiving a pulse signal, the data is expanded to 32K for FFT. When the FFT data is output, it is multiplied pointwise with the clutter data stored in ROM, followed by IFFT. The segments of data are then stored and combined for output through a delay module..
Advantages: Converting the received signal into frequency domain calculations can save a significant amount of DSP resources..
Disadvantages: Using FFT and IFFT consumes a lot of RAM resources, and the first data output occurs after the FFT and IFFT. With a 32k pipelined FFT design, the first data cannot be output until 500us later, and it cannot output all combined signals within 1ms. Additionally, using 16 channels of 32k IFFT resources is insufficient.
Scheme 3
Scheme 3: The clutter data is divided into 16 segments, and 32K is supplemented on the host computer to perform FFT. The generated data is stored in ROM. Upon receiving a pulse signal, the data is expanded to 32K for FFT. When the FFT data is output, it is processed in two paths. The first path matches the timing of the first segment of the pre-stored 256k FFT data and the FFT output data, which is sent to the convolution module in the frequency domain. Simultaneously, the FFT data is stored in two 16k storage spaces.
After Storing 16K Data
The remaining data is stored in another 16k storage space, while the first 16k data is read out and convolved with the frequency domain convolution module..
When the Ping Module Completes Reading the First 16K Data
When the first 16k points are completed, the frequency domain convolution module’s ping part finishes as well, and it starts reading the first 16k area data again for the second convolution operation. When the ping module completes reading the first 32k data, the ping module is halfway through, allowing the convolution data from the ping-pong frequency domain convolution module to be directly combined and output sequentially. The output data stream is shown in the figure above..
Advantages
Advantages: Converting the received signal into frequency domain calculations can save a significant amount of DSP resources. The use of ping-pong operations for convolution saves resources, and this method allows for the consideration of storing 256 FFT data on the PS side in the future..
Disadvantages: It cannot output all combined signals within 1ms.
1/300*(256+16)=0.9067
First, the number of BRAMs required to store 256k of 16-bit convolution data is:
15*2*16=480 units
15——(32k of 16-bit data)
2——IQ data
16——Divided into 16 segments (256k/16k)
The original 16k data needs to be converted into 32k data for FFT, requiring 105 BRAMs.
The data after FFT needs to be stored for ping-pong convolution operations, requiring 57*2=104 BRAMs.
The convolved data needs to be converted into time domain data using 32768 points of IFFT, requiring 98*2=196 BRAMs.
The RF47DR has a total of 1080 RAM units, and the convolution module currently uses 480+105+104+196=885 units, which is about 82% of the total resources.
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