Chip Testing: A Comprehensive Overview

Source: Semika

Original Author: Semika

This article provides a detailed introduction to chip testing.

Chip testing can be broadly divided into two main parts: CP (Chip Probing) and FT (Final Test). Some chips also undergo SLT (System Level Test). Additionally, some specific chips require reliability testing.

CP Testing

CP (Chip Probing) testing, also known as wafer testing, is conducted on the wafer before the chip is packaged. This allows for the identification of defective chips before packaging, saving costs associated with FT. CP testing is positioned between wafer fabrication and packaging in the overall chip manufacturing process. After the wafer is produced, thousands of bare dies are regularly distributed across the wafer. Since the chips have not yet been diced and packaged, all the pins are exposed. These very small pins need to be connected to the tester using finer probes.

The following diagram illustrates the CP automated testing system.

CP can be visualized in the following diagram, where probes are used to test the wafer:

In practice, the number of probes is very large, often using tens of thousands of probes on a probe card. The probe card is designed to hold the wafer, allowing each die and bond pad within the wafer to connect to the probes on the probe card, while also enabling precise shifting. After each test, a different die is connected to the probe card’s probes to ensure every die on the wafer is tested.

CP testing mainly covers the following aspects:

1. SCAN. SCAN is used to verify whether the chip’s logical functions are correct.

2. Boundary SCAN. Boundary SCAN is used to check whether the chip’s pin functions are correct.

3. Memory. Chips often integrate various types of memory (e.g., ROM/RAM/Flash). To test memory read/write and storage functions, BIST (Built-In Self-Test) logic is typically added during design. The chip enters various BIST functions through special pin configurations, and after self-testing, the BIST module feeds the test results back to the tester.

4. DC/AC Test. DC testing includes Open/Short testing of chip signal pins, Power Short testing of power pins, and checking whether the chip’s DC current and voltage parameters meet design specifications.

5. RF Test. For wireless communication chips, RF functionality and performance are crucial. RF testing during CP checks whether the RF module’s logical functions are correct. Further performance testing of RF is conducted during FT.

6. Other Function Tests. Other functional tests of the chip are conducted to verify whether other important functions and performance meet design specifications.

Testing machines need to be selected based on the testing content, with many brands and product series available: for example, memory chips like Advantest T55xx series, digital mixed-signal or SoC chips like Teradyne J750 series, RF chips like Credence ASL-3000 series, etc.

FT (Final Test) Testing

FT (Final Test) is the ultimate test conducted after the chip is packaged. FT testing is a chip-level test that establishes electrical connections between the automated test equipment (ATE) and the packaged chip via a test board (Loadboard) and test socket (Socket). The purpose of FT testing is to filter out products that meet design specifications for sale to customers.

The structure of the FT testing system is illustrated in the following diagram:

The hardware required for FT testing includes a test board, test socket, ATE (Automated Test Equipment), and Handler. The Handler, also known as an automated sorting machine, is used to automate FT testing.

The handler must be combined with the tester and connected to the interface before testing can occur. The action involves the handler’s arm placing the chip into the socket, followed by the contact pusher pressing down. This ensures the chip’s pins make proper contact with the socket, sending a start signal to the tester. After testing is completed, the tester sends back binning and EOT (End of Test) signals. The handler then performs sorting actions.

FT testing items are also determined by the chip’s functions and characteristics. Common FT testing items generally include:

1. Open/Short test, which checks whether the chip pins have open or short circuits.

2. DC test, which checks the device’s DC current and voltage parameters.

3. Eflash test, which checks the embedded flash’s functionality and performance, including read/write parameters, power consumption, and speed.

4. Function test, which tests the chip’s logical functions.

5. AC test, which verifies AC specifications, including the quality of AC output signals and the actual parameters of the signals.

6. RF test, which is aimed at chips with RF modules, primarily verifying the functionality and performance parameters of the RF module.

7. DFT test, which includes DFT (Design for Test) testing, primarily involving scan design and self-testing of internal components, i.e., BIST (Built-In Self-Test).

SLT Testing

SLT stands for System Level Test. SLT is used when the coverage of other tests is insufficient. Additionally, it is used to control costs, as ATE testing can be relatively expensive. SLT testing places the chip on a test board, which can be used to validate the chip’s various functions. By controlling multiple testing machines, batch testing can be achieved.

Hardware required for SLT testing includes test boards, test sockets, Handler, Change Kits, and test hosts with connecting wires. SLT testing is custom testing, with a high degree of flexibility in the software part, not requiring development based on automated testing platforms, and is fully developed by test engineers. SLT testing typically includes chip function testing, high-speed interface testing, and DDR memory-related testing. Similar to FT testing, the program will physically sort the chips into bins based on test results, either Pass or Fail.

In addition to the three main tests mentioned above, some chips may also undergo reliability testing, which includes the following:

1. ESD, which is Electrostatic Discharge testing.

2. Latch-up testing.

3. HTOL, which is High-Temperature Operating Life testing.

4. LTOL, which is Low-Temperature Operating Life testing.

5. TCT, which is Temperature Cycling testing.

6. HAST, which is Highly Accelerated Stress Testing for temperature and humidity.

7. Other specialized testing requirements.

Fully Automated Testing Solutions

Finally, it should be noted that most of the tests mentioned above are often conducted using fully automated testing solutions to improve efficiency, as illustrated in the following diagram.

END

The content is reprinted and only represents the author’s views.

It does not represent the position of the Institute of Semiconductors, Chinese Academy of Sciences.

Editor: Schrödinger’s Cat

Editor-in-chief: Mu Xin

Submission email: [email protected]

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