Recently, the first large-scale fully asynchronous circuit (Asynchronous Circuit) chip designed by the asynchronous circuits and systems team led by Associate Professor He Anping from Lanzhou University’s School of Information Science and Engineering has been successfully taped out.
Fully asynchronous circuit chip (Image from: Lanzhou University)
This chip consists of 120 chips named LZU_GERM, with each small square in the image above representing an independent chip. It is a fully asynchronous multi-core chip designed by the asynchronous circuits and systems team at Lanzhou University, using a 40-nanometer process, integrating 1512 computing units and 350 million transistors within an area of 96 square millimeters, and each chip has a power consumption of only 98 milliwatts. These chips completed their design at the end of April 2021 and were successfully returned in May 2022.
Difference Between Synchronous and Asynchronous Circuits
Currently, the mainstream design of digital chips is synchronous circuits (Synchronous), and its basic structure is shown in the figure below. All units controlled by a clock in the circuit, such as flip-flops (Flip Flop) or registers (Register), are all controlled by a unified global clock. As shown in the figure, flip-flops R1 and R2 are controlled by a unified clock clk, with a set of combinational logic between R1 and R2, which is the simplest synchronous circuit.
It can be said that this clock-driven pipelined structure is the foundation of modern digital circuits. In synchronous design, EDA tools can ensure the timing convergence of the circuit system, effectively avoiding competition and hazard phenomena in circuit design; since flip-flops only change their values at clock edges, the possibility of the entire circuit being affected by glitches and noise is minimized.
However, as the complexity of design and testing continues to increase, coupled with the demand for low-power designs (such as clock gating), issues such as clock skew, clock jitter, and power consumption may arise in a practical design.
Asynchronous circuits are sometimes referred to as clockless or self-timed circuits, and their basic idea is to eliminate the traditional centralized clock control mechanism, adopting a distributed control method to manage and coordinate various functional modules. Specifically, this means ensuring the correctness of data transmission through direct handshake signals (Request and Acknowledge) sent between upstream and downstream stages. Bundled-data is a standard term for this mechanism, meaning that data and control signals are bundled together, where the control signal plays the role of the clock signal in synchronous circuits.
Compared to synchronous clock circuits, the system advantages of asynchronous circuits are reflected in smaller area, lower power consumption, and resistance to electromagnetic radiation; in asynchronous circuit design, the advantages lie in strong modularity, allowing data transmission in the circuit to occur at any time without the problems of clock distribution and clock skew that occur in clock circuit design. However, the challenge is the absence of a clock circuit as the global driving circuit for the chip, and most mainstream commercial EDA software is designed for synchronous circuit design. While there are many excellent synchronous circuit design teams in China, there are very few asynchronous circuit design teams, and even fewer teams capable of producing chips.
As shown in the figure above, flip-flop R1 is controlled by clock clk1, while flip-flop R2 is controlled by clock clk2. The output Q1 of R1 is connected to the input D2 of R2 through combinational logic. The change of the data value at the input of D2 is not under the control of clk2; it may occur at any point in time of clock clk2. In fully asynchronous designs, the advantages of avoiding competition and hazard phenomena, as well as reducing noise influence, that were present in synchronous designs are all lost.
Research on Asynchronous Circuits Started Late in China
Foreign countries have long recognized the advantages of asynchronous circuits and began research, but there has been a strict technological blockade against China. Companies such as Intel and IBM have already demonstrated brain-like computing using asynchronous circuits with chips like Loihi and TrueNorth, which are superior to synchronous circuits of the same period in both power consumption and performance.
The research and development team at Lanzhou University was established in 2013, at a time when domestic asynchronous chip R&D was still in its infancy, and there was a lack of systematic R&D on asynchronous circuits. He Anping led the team over the course of nine years, exploring from asynchronous circuit design methodology to chip design. As early as 2018, He Anping’s team published an academic report titled “Asynchronous Artificial Neural Network Chip Design Method and Implementation” at Lanzhou University.
Based on mainstream commercial EDA software, He Anping’s team gradually broke through a series of chip design issues such as asynchronous driving logic design, asynchronous timing constraints, large-scale asynchronous circuit design, and design stability verification. The team adopted the most advanced asynchronous circuit design methods internationally, and on these small chips, each asynchronous CPU core is connected by an asynchronous mesh network, with data being computed in the CPU and then broadcasted to various routing nodes through the mesh network, and captured by the target routing nodes. This working mechanism is very suitable for the brain-like computing and other high-concurrency computing fields that people are familiar with today.
At the same time, He Anping’s team has developed the EDA software “Puzzle” version 3.0 based on asynchronous circuit design, which has undergone two iterations, becoming the first asynchronous circuit EDA software independently developed in China and is open-sourced on the OpenI website.
Appendix: Resume of He Anping
He Anping, a Ph.D. jointly trained by Lanzhou University and Portland State University in the USA, is a master’s supervisor.
From 2009 to 2011, he conducted research on formal analysis and verification of asynchronous systems under the guidance of Ivan Sutherland (Academician of both the US National Academy of Engineering and the Academy of Arts and Sciences, Turing Award winner in 1988 and Kyoto Prize winner in 2012) and Marly Roncken (Senior Engineer at Intel) at the ARC team at Portland State University. Since 2014, he has independently conducted research on asynchronous system design and analysis verification. He has successfully developed fully asynchronous RSA chips, fully asynchronous SNN chips, and CNN chip demos, published 6 SCI-indexed papers, translated 3 foreign works (2 of which have been completed and are awaiting publication, and 1 has been purchased for translation), participated in 1 chapter of an English book, and authored over 30 indexed papers, including 1 demo paper at a top conference on asynchronous systems, 1 fresh idea paper, 1 CCF Class B conference paper, 1 Class C conference paper, and 3 papers co-authored with Turing Award winners, applied for 16 patents and software copyrights (6 of which have been approved), received a provincial-level second prize for scientific and technological progress, and a youth fund from the National Natural Science Foundation (which has been completed), participated in the formulation of the national standard for Verilog hardware description language, and guided graduate students to win third prizes in competitions organized by the Ministry of Education and the Electronic Society twice, and participated as a main researcher in 7 projects funded by the National Natural Science Foundation, the Ministry of Industry and Information Technology, and other provincial and ministerial projects.
The content of this article references reports from the School of Electronics and Information Engineering at Lanzhou University, Lanzhou News Network, China National Radio, Gansu Audio-Visual, and Science Network.
References:
Can the “Legendary” Asynchronous Circuit Stand Out in the AI Chip Field?——Zhihu @ Tang Shan
Synchronous Circuit, Asynchronous Circuit Design——Blog Garden @ Real Ma Zhui
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