As the parameters of AI large models exceed one trillion and the GPU computing race enters the “EFLOPS era,” the enhancement of chip performance can no longer rely solely on process miniaturization—advanced packaging technology is becoming the “second growth curve.”
For instance, integrating multiple small chips (Chiplets) like building blocks can enhance performance by three times compared to a single chip; using copper-copper hybrid bonding instead of traditional bumps allows for an interconnection density of 100,000/mm², equivalent to placing 100,000 hair-thin wires in the area of a fingernail… These seemingly “microscopic operations” are the magic of advanced packaging.
However, behind this magic lie significant challenges: signal crosstalk, chip overheating, current-induced line breakage, substrate deformation and cracking… The traditional “trial and error” method is not only costly but also cannot keep pace with the iteration speed of AI chips. A report released by Changdian Technology (the third largest packaging and testing company globally and the largest in China) reveals four core challenges of advanced packaging and points out that “simulation technology” has become the key to breaking through these challenges. Today, we will explain in simple terms why advanced packaging is important, where the difficulties lie, and how domestic companies are using simulation technology to break through.
1. First, let’s understand: What is advanced packaging? Why is it indispensable for AI chips?
In simple terms, packaging is the “house” for chips—transforming bare chips cut from wafers into finished products that can be mounted on motherboards through interconnection, packaging, and testing. However, “advanced packaging” is not just a simple shell; it enhances chip performance to a new level through “high-density integration.”
Why is advanced packaging so important now? Because process miniaturization has reached its limits—after 7nm and 3nm, the cost of breaking through to 1nm increases exponentially, while advanced packaging can achieve performance improvements that are “process-independent” through “system integration”:
2.5D/3D stacking: Stacking logic chips and memory chips (HBM) together through silicon interposers reduces data transmission distance by 80% and increases bandwidth by five times;
Chiplet: Splitting a large chip into multiple small chips allows for replacing only the small chip when it fails, reducing costs by 40% and enabling flexible combinations of different functions;
Co-packaged optics (CPO): Integrating optical chips and computing chips in the same package reduces AI server power consumption by 30% and doubles bandwidth.
As a leading packaging and testing company in China, Changdian Technology has laid out five core advanced technologies covering key scenarios such as AI, high-performance computing, and storage:
| Technology Type | Core Advantages | Application Scenarios |
|---|---|---|
| Copper-Copper Hybrid Bonding | Interconnection density of 100,000/mm², replacing traditional bumps | AI chips, high-end SoCs |
| Silicon Interposer | 10μm ultra-fine TSV holes, supporting more than three layers of 0.6μm metal layers | 2.5D integration, HBM pairing |
| Glass Substrate Packaging | Strong heat resistance, low thermal expansion coefficient, supporting large sizes over 100mm | Ultra-large chips, heterogeneous integration |
| Fan-out Panel Level Packaging | 600mm large substrate, area utilization rate over 90% | Consumer electronics, automotive electronics |
| Co-packaged Optics (CPO) | Integration of optical chips and computing chips, reducing interconnection losses | AI servers, data center switches |
2. The 4 Major “Life-and-Death Challenges” of Advanced Packaging: Each Could Render Chips Useless
As advanced packaging progresses towards “high density and heterogeneity,” the technical difficulties increase geometrically. Changdian Technology’s report points out that the industry currently faces four core challenges, each of which directly affects chip yield and reliability:
1. Electrical Performance Challenge: Signal “Crosstalk,” Unstable Power Supply, Wasted AI Computing Power
The higher the interconnection density of chips, the thinner the lines (now down to 0.6μm, 100 times thinner than a human hair), making signal and power supply issues more prominent:
Signal Integrity (SI): When multiple lines are too close, signals can “crosstalk” (interfere), reflect, and lose, leading to data transmission errors in AI chips, such as deviations in GPU computation results;
Power Integrity (PI): AI chips experience significant current fluctuations, and power supply noise can cause voltage to fluctuate, which can lead to performance instability or even system crashes.
For example, a certain AI chip using traditional packaging experienced a data transmission error rate of 10⁻⁶ due to signal crosstalk, meaning that for every one million data sets transmitted, one set was incorrect, making it unsuitable for large model training—this must be resolved by optimizing line layouts and increasing shielding layers.
2. Thermal Challenge: From “Hand Warmers” to “Little Heaters,” Chips Overheating Will Fail
The power density of AI chips is “soaring”: from 100W/cm² for traditional chips to 1kW/cm² for AI chips, equivalent to placing a 1000W electric stove in the area of a fingernail—3D stacking can also “trap” heat inside, with local temperatures exceeding 200℃, far exceeding the chip’s rated temperature of 125℃.
For instance, a certain CPO optical engine (a key component of AI servers) was originally designed for a temperature of 85℃, but during actual testing, the PIC chip temperature reached 85.4℃, and overheating can lead to optical signal attenuation and data transmission interruptions.
3. Electromigration Challenge: Excessive Current Can “Hollow Out” or “Grow Spikes” in Lines
When current density exceeds limits, the atoms in metal lines (such as copper) can be “washed away” by the current, leading to two fatal problems:
At the cathode side (current outflow end): Atom loss forms voids, causing lines to thin or even break, leading to open circuits in chips;
At the anode side (current inflow end): Atom accumulation forms “whiskers” that grow out like hair, causing short circuits with adjacent lines.
Changdian Technology’s tests found that copper bumps in a certain chip would show voids after an average of 1000 hours at 6A current and 90℃—while AI chips need to operate stably for 10 years, this must be predicted in advance through simulation to determine current limits.
4. Warpage Challenge: Multi-Process Leads to “Deformation,” Causing Chip Breakage or Layer Separation
Advanced packaging requires more than 12 processes (gluing, electroplating, curing, grinding, etc.), and temperature and pressure changes at each step can create stress in the substrate, ultimately leading to “warpage”:
Slight warpage can misalign subsequent processes (such as chip mounting);
Severe warpage can cause chip breakage or interlayer separation (for example, PI glue and EMC encapsulation material separating), leading to direct waste.
For example, Changdian Technology’s 2.5D fan-out packaging experienced substrate warpage of 4mm during glass peeling and grinding processes, far exceeding the equipment’s 0.5mm tolerance, resulting in 50% of products being unable to proceed to the next step.
3. Simulation Technology Becomes the “Key to Solutions”: From “Trial and Error 100 Times” to “Getting It Right the First Time”
In the face of these challenges, the traditional “draw blueprints → make samples → test → modify” trial-and-error method is not only costly (with a single sample costing over 100,000 yuan) but also slows down the R&D cycle by 6-12 months. Multi-physics simulation technology can “virtually build chips” on a computer, predict problems in advance, and optimize designs, becoming the “core tool” for advanced packaging.
Changdian Technology has solved multiple key issues through four major simulation directions, and we will look at actual cases:
1. Electrical Simulation: Preemptively “Check” Signal and Power Issues, Reducing Error Rates by 90%
By building a packaging – PCB system-level simulation model, simulating signal transmission and power distribution:
Signal simulation: Analyzing crosstalk, reflection, and transmission loss, optimizing line spacing and shielding design, reducing the signal error rate of a certain AI chip from 10⁻⁶ to 10⁻¹²;
Power simulation: Predicting power noise and voltage drop (IR Drop), adjusting power network layout, reducing voltage fluctuations of a certain chip from ±5% to ±2%.
2. Thermal Simulation: Optimizing Structure and Materials, Reducing CPO Chip Temperature by 10℃
For high thermal density scenarios such as CPO and 3D stacking, thermal simulation predicts temperature distribution:
Case: Changdian Technology conducted thermal simulation on the CPO optical engine, optimizing the thickness of TIM (thermal interface material) and the material of the lid, reducing the original PIC chip temperature from 85.4℃ to 75.1℃, while the temperatures of TIA, Driver, and other chips also dropped by 8-12℃, fully meeting design requirements;
Key: Simulation can also predict “hot spots,” allowing for the preemptive addition of cooling holes or heat sinks in hot areas to avoid local overheating.
3. Electromigration Simulation: Predicting Current Limits to Avoid Line “Breaks or Shorts”
Using electromigration simulation models combined with accelerated experimental data:
Predicting the maximum safe current at different temperatures, for example, the safe current for a certain copper bump at 100℃ is 3.35A, and at 110℃ it is 2.07A, providing a basis for chip design;
Analyzing current density distribution, optimizing line width and shape to avoid excessive local current leading to failure.
4. Warpage Simulation: Matching Test Data, Reducing Scrap Rate by 30%
For multi-process warpage issues, Changdian Technology developed a full-process warpage simulation:
Method: Using the “unit life and death method” to simulate stress changes across 12 processes, considering the viscoelasticity of polymer materials, while simplifying complex structures such as micro bumps and RDL (redistribution layer) to ensure simulation efficiency;
Effect: The deviation of simulation results from test data is less than 10%, allowing for adjustments to process parameters in critical processes such as glass peeling and grinding, reducing substrate warpage from 4mm to below 1mm, and decreasing product scrap rate by 30%.
4. Industry Summary: Advanced Packaging Enters the “Simulation-Driven” Era, Domestic Companies Have Taken the Lead
1. Technology Trends: From “Single Packaging” to “Heterogeneous Integration,” Challenges Focused on “Multi-Physics Coupling”
Packaging Forms: Evolving from 2D planar to 3D stacking/Chiplet, and then to co-packaged optics and multi-dimensional heterogeneous integration, the technical complexity is increasing exponentially;
Core Contradiction: No longer just a single electrical or thermal issue, but the coupling of electrical, thermal, mechanical, and optical multi-physics, for example, temperature increases caused by current can exacerbate electromigration, and temperature changes can lead to warpage, making traditional single simulations inadequate.
2. Competitive Landscape: International Giants Lead in High-End, Domestic Companies Breakthrough in Mid to High-End
International: Intel (Foveros), TSMC (CoWoS), and Samsung (HBM packaging) lead in high-end fields such as 3D/Chiplet and hybrid bonding;
Domestic: Companies like Changdian Technology and Tongfu Microelectronics have made breakthroughs in 2.5D, Chiplet, and CPO technologies, narrowing the gap with international giants through simulation technology, but still need breakthroughs in EUV-related packaging and ultra-high-density hybrid bonding.
3. Key Conclusion: Simulation Technology Becomes a “Necessary Tool”; Without Simulation, There Is No Advanced Packaging
The traditional trial-and-error method accounts for 40% of R&D costs, while simulation can shorten the R&D cycle by 50% and reduce costs by 30%, becoming the “infrastructure” for advanced packaging;
In the future, simulation will develop towards “full-process collaboration,” achieving “digital twins” from design, manufacturing to testing, for example, completing the entire packaging process in simulation and then directly guiding production.
Conclusion: Advanced Packaging Is an Opportunity for “Chinese Chips”; Simulation Technology Is the “Key”
As process miniaturization encounters bottlenecks, advanced packaging becomes the key path to enhancing chip performance without relying on EUV, which is a significant opportunity for the domestic chip industry—because the core competitiveness of packaging lies in process integration and simulation capabilities, rather than “bottleneck” equipment like photolithography machines.
Changdian Technology’s practice proves that through simulation technology, domestic companies can rapidly break through in advanced packaging, moving from “catching up” to “running alongside.” In the future, as the demand for packaging in AI and high-performance computing continues to explode, companies mastering “advanced packaging + simulation technology” will gain a competitive edge in the next round of competition in the chip industry.