Introduction to Cache
Cache is a block of memory in ARM that can be accessed at high speed. Each cache block contains:
1. Main memory address information;
2. Cached data.
Cache can significantly increase the average speed of memory access. Cache has the following two characteristics:
1. Access locations are spatially limited.
An access to one location is likely to be followed by accesses to adjacent locations. Examples of this principle are:
- Sequential instruction execution.
- Accessing a data structure.
2. Access to data is temporary and can change at any time.
An access to an area of memory is likely to be repeated in a short time period. An example of this principle is the execution of a software loop.
To greatly reduce cache control information, multiple locations are combined into a larger location for caching. This larger location is called a cache line, which can be understood as the smallest unit of memory caching (it is easy to understand that you cannot cache every bit). This can reduce the time for subsequent loading and storing, thus leading to an overall performance improvement.
When the data the CPU wants to access is cached in the Cache, it is called a cache hit; when the data the CPU wants to access is not cached in the Cache (the CPU can only read from actual memory), it is called a cache miss.
Typically, caches can manage themselves and update automatically. Whenever a Processing Element (PE) accesses cacheable memory, it first retrieves data from the cache. If a cache hit occurs, data is retrieved from the cache; otherwise, it accesses the memory. ARMv8 allows the use of different cache topologies and access policies.
However, caches can also bring some issues because
when caches exist, accessing a memory address may not yield the expected data.
Data may exist in multiple physical memories;
Memory Hierarchy
As shown in the figure above, memory accesses that are closer to the PE are usually faster, but the memory size is smaller and the cost is higher. In other words, memory components that are further away from the PE can have larger memory blocks and lower prices.
The ARMv8 memory system can select multiple suitable storage devices based on the size and cost of memory blocks to achieve higher utilization value.
Instructions and data can be stored in separate cache lines or in separate cache lines. Each level of cache can have one or more separate instruction and data caches. In the cache topology, consistency is defined using Point of Unification (PoU), Point of Coherency (PoC), and Point of Persistence (PoP).
Cacheability and Shareability Memory Attributes
Cacheability and shareability are two attributes of memory in a multi-core system, defined as follows:
Cacheability This attribute defines whether memory locations are allowed to be allocated into a cache or not. Cacheability is defined independently for Inner and Outer Cacheability locations.
Shareability This attribute defines whether memory locations are shareable between different agents in a system. Marking a memory location as shareable for a particular domain requires hardware to ensure that the location is coherent for all agents in that domain. Shareability is defined independently for Inner and Outer Shareability domains.
Cacheability indicates whether memory can be cached;
Shareability indicates whether memory can be shared among different tasks in the same system;
The Impact of Caches on Applications
In general, caches are invisible to applications, but when memory consistency issues arise, caches need to be considered. This usually occurs when:
1. When memory blocks are not using hardware consistency management and are updated by other agents in the system;
2. When memory blocks are not using hardware consistency management and are updated by other visible application software;
For example, in DMA memory access without hardware consistency management, when a hardware device reads data stored in the cache while the PE writes new data to that location, data consistency cannot be guaranteed, and the hardware device will read old data.
Data Consistency Issues
Software can ensure data consistency through the following methods:
1. Using non-cacheable memory or passthrough mode;
2. The system does not enable caches;
3. Managing cache consistency issues through cache instructions;
4. Ensuring data access consistency through hardware consistency mechanisms.
References:
“ARM Architecture Reference Manual, for ARMv8-A architecture profile” B2.4 Caches and memory hierarchy;
Please feel free to correct any errors.