Produced by Zhineng Zhixin
SiFive launched a new second-generation smart series processor IP in September, covering everything from compact control cores to large-scale matrix engines.
Compared to the previous generation, the new series has improvements in functionality, power consumption control, interface design, and memory management, primarily to meet the rapidly growing demand for AI computing while also adapting to low power consumption and high concurrency scenarios.
This generation of products expands the range of applications and enhances the position of RISC-V in the global computing industry. SiFive is gradually building an open and competitive ecosystem, creating a coexistence with existing architectures like Arm and Intel.
Part 1
Architecture Upgrades and Technical Details
A notable change in the second-generation smart series is the broader coverage of the product line.
SiFive retains the X200 to XM foundation from the first generation while adding a smaller X100 core, available in both 32-bit and 64-bit options.
These small cores are quite practical in embedded devices and low-power scenarios, such as IoT control nodes or sensor modules. The high-performance X390 and XM series have significantly improved in matrix engine scale and computing power, clearly targeting AI inference and training.
Interface design has also seen improvements. SiFive has strengthened the roles of SSCI (Scalar Coprocessor Interface) and VCIX (Vector Coprocessor Interface) in the new series.
◎ SSCI can directly use CPU registers to drive accelerators through custom instructions, reducing control latency;
◎ VCIX accesses vector registers through high-bandwidth channels, suitable for processing large amounts of parallel data.
This design reduces the communication burden between the main core and coprocessors, providing hardware support for rapid adjustments in AI tasks.
Instruction optimization has also seen minor improvements.
For example, the new series adds dedicated instructions for exponential functions, reducing the computation that originally required 15 to 22 instructions down to one. Although this is not a major part of computing power, it can save considerable computation time and improve efficiency in machine learning involving many nonlinear functions.
In terms of memory management, SiFive has replaced the L3 cache from the first generation with an optional shared L2 cache, maintaining a capacity of 1MB but with more reasonable area and energy consumption.
Combined with loosely coupled scalar-vector pipelines and adjustable VLDQ functionality, the system can effectively mask memory latency under known conditions. This is crucial for real-time control applications, ensuring that predictive tasks run smoothly.
Additionally, the introduction of the RVA23 standard aligns the X280 and above cores with the software ecosystem.
In the past, a challenge for RISC-V was the lack of a unified instruction set, requiring developers to adjust for different vendors, which easily led to software fragmentation. The launch of RVA23 paves the way for building an ecosystem similar to Arm’s “minimum general set,” facilitating future promotion.
Part 2
Industry Positioning and Competitive Landscape
SiFive’s strategy for this generation of products has dual aspects.
◎ Emphasizing the low power consumption and versatility of small cores, suitable for the control parts of complex systems;
◎ Using the XM matrix engine, attempting to directly enter the AI acceleration market.
This layout allows SiFive to serve both edge and central computing, finding its market position. A comparison with Arm is inevitable.
Arm relies on an authorization model, dominating the market with a mature ecosystem and rich case studies.
SiFive leverages the openness of RISC-V, providing chip companies with more freedom to use existing IP directly or make deep modifications to standards. With increasing cost pressures and differentiated demands, this flexibility is quite attractive.
Compared to Intel’s Atom or Xeon D, SiFive does not compete on performance metrics but seeks advantages through IP module combinations and interface expansions.
For designs that need to handle general computing, data parallelism, and control logic simultaneously in SoCs, SiFive’s modular solution may be more cost-effective. Especially as AI applications become more diverse, different devices have different needs, and a single large core solution may not suffice.
From an industry implementation perspective, SiFive’s IP has already been seen in mainstream products, including those from Nvidia.
For example, Nvidia’s ConnectX-8 network interface card uses a RISC-V-based data path accelerator. This indicates that SiFive’s value lies not only in performance but also in its practicality as a “general component.” In the future, as manufacturers increasingly value autonomy and cost optimization, RISC-V may see more widespread use.
However, challenges remain.
SiFive lacks sufficient ecosystem support in high-performance computing, as compared to mature tools like CUDA or Arm Compute Library, the developer resources and migration tools for RISC-V are still weak. Moreover, ensuring stability and consistency in process adaptation and large-scale commercialization is a challenge that needs to be addressed in the coming years.
Technically, the second-generation smart series from SiFive has made tangible progress in interfaces, instruction optimization, cache design, and standardization, making it suitable for edge control and AI acceleration.
From an industry perspective, its open and flexible model differs from Arm and Intel, providing manufacturers with new choices.
Conclusion
The second-generation smart series from SiFive represents a deeper step for the RISC-V ecosystem in AI acceleration and low-power computing. With the rapid increase in computing power demand and the growing number of AI applications, this modular and scalable IP solution may become a new direction for system design. In the coming years, SiFive’s success will depend not only on the performance of individual products but also on how it enhances the ecosystem to establish RISC-V in more scenarios.