Hello everyone! Today, we are going to discuss a very practical topic—how to use the MIPI interface on Zhi Duo Jing FPGA. Whether it’s for camera image acquisition or display control, MIPI is a very common interface standard. Mastering it will greatly enhance your video project development efficiency!
The Zhi Duo Jing FPGA supports the use of the MIPI interface mainly through two components: first, the hardware resistor network design, and second, the use of the officially provided MIPI IP cores (including CSI-2 RX and DSI TX). Let’s briefly go over how to get started.
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Important Considerations for Hardware Design!
Whether using the SA5T-100 or SA5Z-30 series FPGA, there are several general principles for hardware design:
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Try to use the HP IO Bank for better performance.
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Connect clock signals to dedicated clock pins.
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Place matching resistors as close to the FPGA pins as possible.
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A VREF reference voltage pin needs to be set, usually at 0.6V.
The specific connection method for the resistor network is clearly illustrated in the official diagram, just follow it, no need to worry!
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IO Constraint Settings are Also Very Important
In FPGA design, IO constraints are key to ensuring signal integrity. The MIPI interface has two modes: HS (High Speed) and LP (Low Power), which require separate level attribute settings.
For example, in the SA5T-100:
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RX side: HS uses LVDS18, LP uses HSUL12;
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TX side: HS uses HSTL18D_I, LP uses LVCMOS18.
In the SA5Z-30:
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RX side: HS uses LVDS25, LP uses LVCMOS12R25;
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TX side: HS uses LVDS25_I, LP uses LVCMOS25.
Don’t worry about these terms; the official example code has ready-made templates, just copy and paste and change the pin names!
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Zhi Duo Jing MIPI IP Cores for Rapid Development
To help everyone get started with MIPI faster, Zhi Duo Jing provides two very useful IP cores:
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CSI-2 RX IP: for receiving camera data;
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DSI TX IP: for outputting video to displays.
Both IPs offer a graphical configuration interface, allowing you to easily set parameters such as channel count, pixel format, and transmission rate without needing to delve into the underlying protocols, truly achieving “plug and play”.
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Conclusion
With reasonable hardware design, correct IO constraints, and the MIPI IP cores provided by Zhi Duo Jing, you can easily implement MIPI interface video data transmission on FPGA. Whether for image processing or display driving, you can achieve great results with less effort!
If you’re interested, give it a try! If you have any questions, feel free to leave a comment for discussion, and for specific usage issues, please contact Zhi Duo Jing FAE for professional technical support.
