Learn How to Get Started with FPGA Programming Language

When learning FPGA, the first thing we need to study is the programming language for FPGA. Unlike the “high-level” languages such as C, C++, and Java used in software development, the language used for FPGA development is called Hardware Description Language (HDL), or Register Transfer Level (RTL) language.

The mainstream hardware description languages are VHDL and Verilog, and there is also one called SystemVerilog. Each of VHDL and Verilog has its own advantages and disadvantages; for example, VHDL has a more rigorous syntax, while Verilog is more flexible and resembles C language. It is recommended to start with Verilog, especially if you have a certain foundation in C language, as it should be easier to grasp. After you accumulate some development experience, you can consider looking into VHDL. This is because, in actual projects, some modules may be written in Verilog while others are written in VHDL, and even if you are not very familiar with what you wrote in VHDL, you should still be able to understand the design written in VHDL.

No matter what language you are learning, the main learning content generally consists of three major parts: the first is syntax, the second is how to design circuits using this language, and the third is how to use this language for verification.

There are countless books on Verilog syntax, but in fact, the content is mostly similar, so there is no need to get too caught up in which book to read; just find a well-reviewed one. Some well-known titles include “Verilog Digital System Design Tutorial” and “Verilog HDL Advanced Digital Design.” However, regardless of which book you choose, I suggest you spend time carefully reviewing Verilog syntax; there is no need to memorize it, but you should have a good understanding of the basic usage and functions of each syntax.

The syntax of Verilog can be divided into synthesizable and non-synthesizable parts. Synthesizable refers to the part of the statements that can generate corresponding hardware circuits. If your time is limited, we can first look at the synthesizable Verilog syntax, which is actually not much; the commonly used ones are only about ten statements. After mastering these, we can then look at the non-synthesizable Verilog statements that are mainly used for simulation and verification.

Currently, I do not recommend beginners with no background to self-study SystemVerilog, mainly because I have not found good Chinese introductory materials. However, if your school or training class teaches SystemVerilog, that would be best, as it can provide a comprehensive introduction. A book I have been reading for a long time is called “SystemVerilog Hardware Design and Modeling,” which I bought ten years ago. It is a very good reference book. However, please note that it is not a textbook for SystemVerilog, so if you are just starting out, reading this book will surely confuse you. Once you finish learning Verilog, it will be much easier to transition to SystemVerilog by reading this book.

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