With the rapid development of fields such as artificial intelligence (AI) and high-performance computing (HPC), the demand for chip performance is increasing. Against this backdrop, glass substrate technology, with its excellent physical properties and advanced packaging potential, is gradually becoming a new favorite in the semiconductor industry. The strong promotion by the U.S. government, particularly the recent announcement of funding for companies like Absolics under the CHIPS Act, marks an unprecedented development opportunity for the glass substrate industry.
In the past two years, the continuous maturation of glass substrate technology has gradually uncovered its potential in advanced packaging. Major semiconductor companies globally, such as Intel and Samsung, are actively positioning themselves in glass substrate technology. Intel has announced plans for mass production of glass substrates by 2030 and has invested $1 billion in its Arizona facility to establish a glass substrate R&D line and supply chain. Samsung has formed a unified front with Samsung Electronics, Samsung Display, and Samsung Electro-Mechanics to enter glass substrate R&D. Furthermore, the application areas for glass substrate materials are extensive, including alternatives to CoWoS interposers/FC-BGA substrates, co-packaging of optical device integration, Mini/Micro LED backplane materials, passive devices, and sensor packaging. Now, more leading companies, including BOE and TSMC, are actively exploring glass substrate technology.
By deeply analyzing recent patents related to glass interposers and core substrates in advanced packaging, we can glimpse the current research hotspots and development directions in the field of glass substrates.
1. Patent Landscape of Glass Substrates
According to Knowmade’s statistics, there are currently over 300 patents related to glass interposers and glass core substrates in the advanced packaging field, with major participants including Intel and Absolics, which together account for nearly half of the patents. Over 70 other entities globally have collectively applied for more than 150 patents.
Intel: Leads in patent quantity, holding the most patent applications, with a portfolio covering glass core substrates and glass interposers, showcasing a comprehensive and balanced layout, placing it at the forefront of technological innovation in the industry.
Absolics: Focused on the glass core substrate field, it is Intel’s closest competitor in terms of patent quantity, highlighting its R&D investment and technical strength in this specific area.
Other numerous entities: Over 70 entities collectively hold half of all related patents, but each entity’s patent holdings are relatively small, indicating a highly decentralized situation. This includes TOPPAN, Corning, Hitachi, GlobalFoundries, TSMC, Samsung, Qualcomm, Unimicron, BOE, Huajing Semiconductor, Xiamen Yuntian, Shenghe Jingwei, Tongfu Microelectronics, Guangdong Buzhixin, etc., which also hold a certain share in the patent landscape of the glass substrate industry. From the trend of patent applications, Intel was actively laying out early, continuously accumulating patents since 2004, but has seen a recent surge in numbers. Between 2019 and 2024, many companies have rushed in. For example, Absolics (SK Group) has gradually increased its patent applications, while Samsung, Shenghe Jingwei, Xiamen Yuntian Semiconductor, and others have emerged during this period.
This indicates that the technological innovation and intellectual property competition in the glass substrate industry are intensifying, attracting increasing attention and investment from more enterprises.
Among emerging competitors, companies like Samsung, Shenghe Jingwei, and Xiamen Yuntian Semiconductor have published many patents for the first time between 2019 and 2024, showing a year-on-year upward trend, marking their active exploration and innovative achievements in glass substrate technology R&D and continuous increase in R&D investment, further enriching the technical innovation ecosystem of the industry and driving the entire industry’s patent competition landscape towards diversification.
From a geographical distribution perspective, the leading companies Intel and Absolics have a wide geographical coverage in their patent layout, applying for patents in the U.S., mainland China, Taiwan, South Korea, Japan, and Europe. This global patent layout strategy helps them protect their technological innovations in different markets while reflecting the international competitive landscape of the glass substrate industry.
Samsung mainly applies for patents in the U.S., China, and South Korea, focusing on its technological protection and market competitive advantage in the Asian and North American markets.
Domestic companies have both focused layouts in both domestic and international markets, as well as concentrated layouts in domestic markets. For instance, Shenghe Jingwei’s patent applications are concentrated in the U.S. and China, reflecting its emphasis on these two important markets and its strategic layout in local market competition. Meanwhile, Xiamen Yuntian currently has almost all its patent applications in China, indicating its gradual accumulation of technical strength and intellectual property assets based on a foothold in the local market, laying the foundation for future expansion into broader markets.
2. Research Hotspots in Glass Substrate Technology
– Integration of Glass Substrates and Interposers in Packaging
Transitioning from silicon materials to glass materials requires solving multiple challenges, which are also reflected in patent applications. These include achieving thinner packaging in embedded chips; for chip-to-chip coupling, achieving higher density interconnections; hybrid bonding of chips/glass; and Intel’s research on EMIB, etc.
Among them, innovations in metallization and interconnection technology are one of the research hotspots. For example, high aspect ratio via (TGV) metallization: Developing efficient metallization processes targeting the high aspect ratio characteristics of TGV to ensure uniform filling of metal within the via, preventing voids, improving electrical connection performance, and reducing signal transmission loss; improving metal/glass adhesion: Studying the adhesion mechanisms between metal and glass, enhancing the bonding force through surface treatment or material improvements to prevent delamination or peeling during the packaging process or product use, thereby improving long-term reliability; hybrid bonding technology (chip/glass): Exploring hybrid bonding methods between chips and glass, such as direct Cu/SiO₂ bonding, achieving tighter connections, increasing packaging density, reducing signal delay, while optimizing thermal management performance, providing solutions for high-performance computing and high-density packaging.
Optimizing packaging architecture and enhancing functionality is another major hotspot. For instance, embedded chips (Embedded Die): By embedding chips in glass substrates, achieving thinner packaging structures, reducing packaging volume, and improving product integration to meet the trend of miniaturization and lightweighting in electronic products; chip-to-chip coupling (D2D Coupling): Focusing on enhancing connectivity between chips, developing high-density, high-performance interconnection technologies, such as using micro bumps (µbumps) or interconnect bridges to achieve faster and more stable data transmission, enhancing overall system performance; Intel has introduced the fan-out embedded glass bridge (EMIB) technology for many years: Researching the application of EMIB technology on glass substrates, achieving efficient signal transmission between chips by embedding conductive bridges in glass substrates while optimizing the heat dissipation performance of packaging, enhancing product reliability and performance.
Additionally, co-packaging of photons is also a research hotspot, with half of Intel’s patents focusing on photon integration-related fields. There are also large panel-level packaging solutions with improved cost-effectiveness, as well as patents related to thermal management.
– Manufacturing Processes or Designs of Glass Substrates and Interposers
Patents related to the design and manufacturing of glass substrates and glass interposers mainly cover defect control (quality inspection materials or processes); methods for strengthening thin glass substrates; alignment methods (based on glass transparency); metallization of high AR vias, adhesion between metal and glass; TGV structures and manufacturing; reducing signal crosstalk within interposers; thermal management, etc.
Among them, improvements in manufacturing processes are a research hotspot. This includes innovations in surface treatment technologies: Developing new surface treatment processes targeting the challenges posed by glass surface roughness and TGV’s high aspect ratio, such as directly plating copper on dielectric (without a seed layer) to achieve void-free metal via filling, improving metallization quality and reliability. At the same time, researching technologies like plasma surface activation to enhance the reactivity of the glass surface with metals, improving adhesion performance; stress management and warpage control: By optimizing manufacturing process parameters or adopting special structural designs, addressing stress issues in glass substrates during manufacturing and usage, reducing the risk of warpage deformation. For example, forming cavities in glass core substrates and embedding silicon bridge interposers, effectively reducing the degree of warpage in packaging substrates by utilizing the combined properties of glass and silicon materials, improving product flatness and stability; prefabricated components and simplified assembly processes: Developing prefabricated copper pillars and exploring efficient assembly methods with glass materials, such as manufacturing copper pillars on silicon substrates through electrochemical deposition and then anodically bonding them with glass substrates, avoiding complex and costly electroplating and chemical mechanical polishing (CMP) steps while integrating a passivation layer as a stress buffer layer, improving product reliability and reducing production costs.
Thermal management and optical performance optimization is another major hotspot. For example, designing glass core substrates with fluid channels to achieve effective cooling through the packaging substrate, rather than relying solely on the top chip’s heat dissipation, improving cooling efficiency and ensuring product stability under high-power operating conditions. At the same time, researching designs for thermal conductive sleeves around TGVs to improve thermal conduction paths, preventing crack propagation around vias due to the mismatch of thermal expansion coefficients (CTE) between glass and copper, enhancing the thermal reliability of the product. In terms of optical performance, utilizing the optical transparency of glass to optimize the optical design of glass substrates, such as developing waveguide integration technology to achieve efficient integration of photonic integrated circuits (PIC) and electronic chips (EIC) on glass substrates, improving optical signal transmission efficiency and accuracy, providing better platform support for photonic applications.
3. Key Technical Challenges and Corresponding Patent Solutions
– Mechanical Stress Management (Warpage Issues)
The significant differences in thermal expansion coefficients between glass materials and other packaging materials (such as silicon chips and organic packaging materials) can lead to uneven thermal expansion or contraction during temperature changes in the packaging process, resulting in warpage of the packaging substrate. Warpage issues not only affect the precision and electrical connection performance of the packaging but may also lead to fatigue and cracking of the solder joints between the chip and substrate, severely impacting product reliability and lifespan.
Patent Solutions
Composite structural design: Samsung’s patent (e.g., CN118431173) involves the composite structural design of glass substrates and glass interposers. By optimizing the combination of the two, leveraging the low CTE and high rigidity of glass, effectively reducing the warpage of the packaging substrate.
Cavity and embedded structural applications: Forming cavities in glass core substrates and embedding silicon bridge interposers and other components. This structural design can compensate for thermal expansion differences between different materials to some extent by adjusting internal stress distribution, reducing the risk of warpage deformation and improving the stability and reliability of the packaging structure.
– Glass Surface Treatment
The high roughness of glass surfaces and the high aspect ratio of TGV pose difficulties for the metallization process, making it challenging to achieve uniform, void-free metal deposition on such surfaces, which affects electrical connection performance. The adhesion of metal layers (such as copper) to smooth glass surfaces is poor, leading to peeling or delamination when combined, reducing the reliability of the packaging structure. Additionally, during the packaging process, the movement of glass substrates in processing equipment can also lead to handling difficulties due to adhesion issues.
Patent Solutions
Direct copper plating process innovation: Intel’s patent (US20240213131) proposes a process for directly plating copper on dielectrics without a seed layer. By ionizing the -OH bonds formed on the glass surface to create -O⁻ bonds, achieving high reactivity with metal ions, enabling direct copper plating, effectively solving the conformal metallization issues under high aspect ratios of TGV, avoiding potential void issues in traditional processes, and improving metallization quality.
Surface roughening to enhance adhesion: Another Intel patent (US20240222249) involves roughening the surface of glass core layers. The roughened glass surface can increase the mechanical interlocking force with metal layers, thereby enhancing adhesion between glass and metal, addressing issues of separation between glass and copper features due to adhesion problems and handling difficulties during processing, improving the stability and reliability of the packaging structure.
– Thermal Management
As the performance of electronic products improves and chip power consumption increases, the heat dissipation issues of glass substrates in packaging have become a key challenge. Glass has relatively poor thermal conductivity, and effectively dissipating heat generated by chips to ensure stable operation of products in high-temperature environments is an important issue to address. In glass core substrates or glass interposers, due to the mismatch of thermal expansion coefficients (CTE) between materials, such as glass and copper (commonly used for via filling and circuit connections), thermal stress can easily arise during temperature changes, potentially leading to via cracking and delamination between chips and substrates, among other reliability issues.
Patent Solutions
Glass-based cooling structure design: Intel proposed a cavity and channel structure based on glass (e.g., US20220406686) for cooling embedded chips and 3D integrated modules. By designing fluid channels in glass core substrates, cooling media can flow through the packaging substrate, achieving more comprehensive heat dissipation rather than relying solely on top chip heat dissipation, effectively improving cooling efficiency.
Thermal conductive sleeve applications: Another Intel patent (US20230088392) involves setting thermal conductive sleeves around TGVs. These sleeves are made of materials with higher thermal conductivity than via materials (such as copper), enabling more effective heat conduction away from the chip while avoiding crack propagation around vias due to CTE mismatch between glass and copper, enhancing the thermal reliability of the product.
– Prefabricated Copper Pillar Assembly
In traditional assembly processes of glass substrates with other components (such as chips), the steps of electroplating and chemical mechanical polishing (CMP) are complex and costly, increasing production costs while potentially introducing process defects that affect product quality. Precisely controlling via diameter and glass hole sidewall roughness is crucial for ensuring good electrical connections and reliable bonding between components, but traditional processes face certain difficulties in this regard.
Patent Solutions
Xiamen Yuntian Semiconductor (e.g., CN118412319) proposed a method for manufacturing glass adapter plates, first manufacturing copper pillars on silicon substrates through electrochemical deposition, then anodically bonding the glass substrate to them, followed by filling a passivation layer and adding a metal layer to connect the copper pillars, and finally removing the silicon substrate. This method avoids complex electroplating and CMP steps, reducing costs, while the integrated passivation layer serves as a stress buffer layer, improving product reliability.
Shenghe Jingwei’s molding process (e.g., CN116631876) patent involves an integrated molding manufacturing method for TGV adapter plates. By forming grooves on silicon substrates, performing glass reflow, and then pressing prefabricated metal pillars into the grooves filled with glass liquid, precise control of via diameter is achieved, reducing glass hole sidewall roughness, thus improving adhesion between components and overall product performance.
Conclusion
With the continuous development of emerging technologies such as artificial intelligence, high-performance computing, and photonics, the glass substrate industry will welcome more opportunities. It is expected that more companies will enter this field to participate in competition, accelerating the development of technological innovation, with new patent applications and technological breakthroughs expected to emerge continuously.
In terms of competitive landscape, it is currently still in the early stages and will continue to evolve, with existing companies likely to further increase R&D investment, consolidate and expand their patent portfolios to protect intellectual property and enhance market competitiveness. Meanwhile, new entrants may bring new technological ideas and business models, prompting dynamic changes in the industry landscape.
In terms of technological development trends, the performance of glass substrates will continue to optimize, such as achieving higher heat dissipation efficiency, lower warpage deformation, and superior optical performance. The integration and application of glass substrates with other advanced packaging technologies (such as 3D stacking, hybrid bonding, etc.) will become more widespread.
Source | Jiwei Network
