Formal Verification

Cross-Level Joint Simulation and Verification of Automatic Transmission Control on Embedded Processors

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Cross-Level Joint Simulation and Verification of Automatic Transmission Control on Embedded Processors

AbstractThis study proposes a method for developing cyber-physical systems that starts from a high-level representation of the control algorithm, performs formal analysis of the algorithm, and conducts joint simulation of the algorithm with the controlled system at both high-level (abstracting the target processor) and low-level (including simulation of the target processor). The expected advantages are … Read more

RISC-V Microarchitecture Verification

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RISC-V Microarchitecture Verification

The RISC-V processor has garnered widespread attention due to its flexibility and scalability, but without efficient verification strategies, erroneous design implementations could hinder the continued promotion of RISC-V. Before RISC-V emerged, processor verification had almost become a dragon-slaying skill for most semiconductor companies. Expertise was concentrated in a few commercial companies that provided processors or … Read more