EtherCAT – State Machine

EtherCAT - State Machine

The EtherCAT State Machine (ESM) coordinates the master and slave applications during startup and operation. The state changes of slave devices are usually initiated by requests from the master; however, in some cases, the local applications of the slave can also independently change states. To transition from the Initialization state to the Operational state, EtherCAT … Read more

Implementing State Machine Design Pattern in C Language

Implementing State Machine Design Pattern in C Language

The state machine pattern is a behavioral pattern that effectively implements different state transition behaviors through polymorphism. Unfortunately, in embedded environments, it is often necessary to write pure C code, while also considering reentrancy and multitasking request transitions, making the implementation quite challenging. Recently, while reviewing an open-source system, I came across an implementation of … Read more

A Complete Guide to Function Pointers in C: From Basics to Advanced Applications

A Complete Guide to Function Pointers in C: From Basics to Advanced Applications

Function pointers are a powerful feature in the C programming language, allowing programs to pass, store, and dynamically call functions as data, providing great flexibility in code design. This article will systematically explain function pointers from their definition syntax, basic usage to advanced applications (callback mechanisms, state machines, plugin systems, object-oriented simulation), combining core insights … Read more

MultiButton: A Lightweight and Flexible Multi-Key State Library

MultiButton: A Lightweight and Flexible Multi-Key State Library

Think about it, when you’re working on IoT projects or DIY gadgets, handling various button events can turn your code into a mess… Is there a tool that can handle press, release, single click, double click, long press, and repeated presses all at once? Today, I want to recommend an efficient tool that I’ve been … Read more

Avoiding Callback Hell in C Programming

Recently, I came across a very interesting term “callback hell”, which refers to the endless nesting of callback functions that ultimately leads to stack overflow and deadlock. The manifestation of this is multiple layers of nested function pointer callbacks, resulting in poor code readability and maintenance difficulties.Below is a simple example simulating asynchronous file reading … Read more

In-Depth Analysis of Design Patterns in C Language Embedded Programming

In-Depth Analysis of Design Patterns in C Language Embedded Programming

Supplementing the Previous Article on the Observer Pattern: Application of Embedded Design Patterns in the Observer Pattern In resource-constrained embedded system development, the application of design patterns can significantly enhance the maintainability, reliability, and execution efficiency of the code. Although C language does not support object-oriented features, various design patterns can still be implemented through … Read more

My 7th Lesson on FPGA: Accessing Flash Memory with a Mature SPI Controller

My 7th Lesson on FPGA: Accessing Flash Memory with a Mature SPI Controller

The SPI interface (Serial Peripheral Interface) is a synchronous serial communication protocol widely used for high-speed data exchange between devices over short distances. Its core features and technical details are as follows: Communication Modes Uses a master-slave architecture, supporting communication between a single master and one or more slave devices, with the master device managing … Read more

SystemVerilog Syntax: Learn a Bit Every Day to Enhance RTL Development Efficiency (Part 2)

SystemVerilog Syntax: Learn a Bit Every Day to Enhance RTL Development Efficiency (Part 2)

Introduction In the field of digital circuit design, it is commonly believed that Verilog is a design language, while SystemVerilog is specifically a verification language that cannot be used for design. However, this notion is inaccurate! In fact, SystemVerilog is also suitable for design and, in some aspects, even more convenient than Verilog. One of … Read more

Intermediate PLC Programming: Mastering Finite State Machine Design for Complex Processes!

Intermediate PLC Programming: Mastering Finite State Machine Design for Complex Processes!

🔥 What Are the Limits of Traditional Logic Programming? The Magical Charm of Finite State Machines! Is your PLC program bloated due to complex process flows? Difficult to debug? Frequent failures? Is every upgrade like defusing a bomb? Today, I will reveal a programming tool known as Finite State Machine (FSM) that will help you … Read more