Introduction

In the field of digital circuit design, it is commonly believed that Verilog is a design language, while SystemVerilog is specifically a verification language that cannot be used for design. However, this notion is inaccurate! In fact, SystemVerilog is also suitable for design and, in some aspects, even more convenient than Verilog. One of the main goals of SystemVerilog at its inception was to create synthesizable complex hardware design models more accurately while using fewer lines of code to achieve this goal. SystemVerilog-2005 is not an independent language; it is merely a set of extensions on top of Verilog-2005. In 2009, IEEE officially renamed <span>Verilog</span> to <span>SystemVerilog</span>. It is worth noting that SystemVerilog is backward compatible with Verilog, and you can use SystemVerilog syntax simply by changing the file extension from .v to .sv.

The Easiest State Machine Tool

When designing state machines, it is necessary to define state parameters. In the definition of state parameters, if there are duplicates, ordinary Verilog coding cannot detect this at compile time. Such issues may only be discovered after simulation or board testing. However, using the enum (enumeration) type can timely identify these problems at the compilation stage, thereby improving the reliability of the code and the efficiency of debugging.

The enum type in SystemVerilog has some strict rules:

• • The label values must be the same size as the variable: When defining the enum type, the size of the binary representation for each label (i.e., enum value) is specified. When used, the value assigned to the enum variable must match this size. This ensures the valid range of values for the enum variable.
• • Can only be assigned labels from the enum list: Enum variables can only be assigned label values listed in the enum type definition. This prevents variables from being assigned invalid or irrelevant values.
• • Can be assigned the label value of another variable of the same enum type: It is allowed to assign an enum variable the label value of another variable of the same enum type. This helps in passing and comparing enum states within the program.
• • Other assignment operations are illegal: Apart from the specified cases above, any other assignment operations are illegal. This restriction ensures the strictness of the enum type, preventing confusion or erroneous assignments between different types.

In the code below, the values of WAIT and DONE are the same, which is clearly an error, but Verilog cannot detect it. However, using enum, this can be checked immediately during compilation or through syntax checking tools.

Verilog Implementation

parameter [2:0] WAIT = 3'b001,   
                LOAD = 3'b010, 
                DONE = 3'b001;
parameter [1:0] READY = 3'b101,
                SET = 3'b010,
                GO = 3'b110;

reg [2:0] state, next_state; 
reg [2:0] mode_control; 

always @(posedge clk or negedge rstN)
    if (!resetN) 
        state <= 0;
    else
        state <= next_state;

always @(state) // next state decoder
    case (state)
        WAIT : next_state = state + 1;
        LOAD : next_state = state + 1;
        DONE : next_state = state + 1;
    endcase

always @(state) // output decoder
    case (state)
        WAIT : mode_control = READY;
        LOAD : mode_control = SET;
        DONE : mode_control = DONE;
    endcase

SystemVerilog Implementation

enum logic [2:0] {
    WAIT = 3'b001,
    LOAD = 3'b010,
    DONE = 3'b001
} state, next_state;

enum logic [1:0] {
    READY = 3'b101,
    SET = 3'b010,
    GO = 3'b110
} mode_control;

always_ff @(posedge clk or negedge rstN)
    if (!resetN) 
        state <= 0;
    else
        state <= next_state;

always_comb // next state decoder
    case (state)
        WAIT : next_state = state + 1;
        LOAD : next_state = state + 1;
        DONE : next_state = state + 1;
    endcase

always_comb // output decoder
    case (state)
        WAIT : mode_control = READY;
        LOAD : mode_control = SET;
        DONE : mode_control = DONE;
    endcase

Multiple Drivers

In Verilog, the issue of multiple drivers can usually only be discovered after synthesis, which delays the exposure of the problem and increases debugging costs. In SystemVerilog, with its stricter type system and enhanced compilation checking mechanisms, we can capture multiple driver errors during simulation or compilation, greatly enhancing design safety and development efficiency.

module multi_driver_sv;
  logic a;
  initial a = 1'b0;
  always #5 a = ~a;       // First driver
  always #10 a = 1'b1;    // Second driver (compilation or simulation directly reports an error)
endmodule

Conclusion

Next, we will introduce a type tool that is <span>defined once and used everywhere</span>, bringing more convenience to your design. We will continue to present SystemVerilog syntax in a relaxed, short, and chaptered manner to lower the learning threshold and enhance practical efficiency.

Previous Reviews

SystemVerilog Syntax: Learn a Bit Every Day to Enhance RTL Development EfficiencyReflections from a 20-Year Senior FPGA Engineer at Nokia: What Kind of FPGA Talent Do We NeedFPGA/IC Development Protocol Manual (RDMA): Understand What RDMA Is in One ArticleEthernet – FPGA Design of Network Packet Parser (5)

Appendix A

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Appendix C

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