data delay

Introduction to FPGA: Implementing Shift Registers with Verilog/VHDL

by
Introduction to FPGA: Implementing Shift Registers with Verilog/VHDL

What is a shift register? In FPGA (or ASIC), a shift register is a very common basic module. Its essence is to connect multiple flip-flops (registers) in a chain. All flip-flops share the same clock signal, and the output of each flip-flop is connected to the input of the next flip-flop. In this way, data … Read more