Click the card below to follow Arm Technology Academy This article is selected from the Jishu column “Lingdong MM32MCU” and is authorized to be reproduced from the WeChat public account Lingdong MM32MCU. The previous article introduced Cortex-M0 Interrupt Control and System Control (Part 1), this article will continue to introduce the knowledge of Cortex-M0 interrupt … Read more
This article is selected from the “Smart MM32MCU” column of Jishu, authorized for reprint from the WeChat public account Smart MM32MCU. The previous article introduced Cortex-M0 Interrupt Control and System Control (Part 1), and this article will continue to introduce the knowledge of Cortex-M0 interrupt control.. Each external interrupt has a corresponding priority register. There … Read more
This article is reproduced from the Jishu Community Jishu Column: Agile MM32 MCU Each external interrupt has a corresponding priority register. The Cortex-M0 has a total of 8 NVIC-IPR registers, with each register managing 4 IRQ interrupts. Therefore, the M0 supports a maximum of 32 IRQ interrupt sources, plus 16 core interrupts, which means the … Read more
Today, Pi Zi Heng will share with you the three implementations of critical section protection in Cortex-M bare metal. Those who have worked with embedded systems and RTOS are likely familiar with the function codes OS_ENTER_CRITICAL() and OS_EXIT_CRITICAL(). In RTOS, multi-tasking (process) handling often occurs, and in some situations, certain special operations (such as Flash … Read more
Source | Pi Zi Heng Embedded Today, I will share with you three implementations of critical section protection in Cortex-M bare metal environments. Friends who have worked with embedded systems and RTOS are probably very familiar with the functionality codes OS_ENTER_CRITICAL() and OS_EXIT_CRITICAL(). In an RTOS, there are often multi-task (process) handling situations where certain … Read more