This article is reproduced from the Jishu Community Jishu Column: Agile MM32 MCU Each external interrupt has a corresponding priority register. The Cortex-M0 has a total of 8 NVIC-IPR registers, with each register managing 4 IRQ interrupts. Therefore, the M0 supports a maximum of 32 IRQ interrupt sources, plus 16 core interrupts, which means the … Read more
Hello everyone, I am Pi Zi Heng, a serious technical enthusiast. Today, I will share with you three implementations of critical section protection in Cortex-M bare metal environment. Friends who have worked with embedded systems and RTOS must be familiar with the function codes OS_ENTER_CRITICAL() and OS_EXIT_CRITICAL(). In RTOS, there is often multi-tasking (process) handling, … Read more
Today, Pi Zi Heng will share with you the three implementations of critical section protection in Cortex-M bare metal. Those who have worked with embedded systems and RTOS are likely familiar with the function codes OS_ENTER_CRITICAL() and OS_EXIT_CRITICAL(). In RTOS, multi-tasking (process) handling often occurs, and in some situations, certain special operations (such as Flash … Read more
Source | Pi Zi Heng Embedded Today, I will share with you three implementations of critical section protection in Cortex-M bare metal environments. Friends who have worked with embedded systems and RTOS are probably very familiar with the functionality codes OS_ENTER_CRITICAL() and OS_EXIT_CRITICAL(). In an RTOS, there are often multi-task (process) handling situations where certain … Read more