Chip Hardware Cost
The hardware cost of a chip includeswafer cost + mask cost + packaging cost + testing cost four parts, which can be summarized as the hardware cost of a chip = (wafer cost + mask cost + packaging cost + testing cost) / final yield rate.
A wafer is the raw material for manufacturing chips,wafer cost can be understood as the cost of the material (silicon wafer) used for each chip. When the production volume is large enough, calculated in hundreds of millions, the wafer cost accounts for the highest proportion of the hardware cost.
Mask cost is the cost incurred by using different process technologies. For example, the 40/28nm process is already very mature, with the mask cost for the 40nm low-power process being $2 million; the 28nm SOI process costs $4 million; and the 28nm HKMG costs $6 million. However, the most advanced process technology comes at a sky-high price. When the 14nm process was first put into production in 2014, the mask cost was $300 million; the next generation 10nm process, according to Intel’s official estimate, requires at least $1 billion for the mask cost.
Packaging cost refers to the cost of stacking the substrate, core, and heat sink together to create the chips we see every day. In this process, the packaging cost generally accounts for about 5%-25% of the hardware cost, although for some IBM chips, the packaging cost can account for about half of the total cost, and it is said that it has reached as high as 70% at times.
Testing cost refers to the cost of testing the characteristics of each chip, such as maximum frequency, power consumption, heat generation, etc. It also includes the cost incurred when determining the chip grade, for example, Intel classifies a batch of chips into categories like: I5 4460, I5 4590, I5 4690, I5 4690K, and sets different prices for them. However, the testing cost occupies a very small proportion, and if the chip production volume is large, it can even be negligible.
Chip Design Cost
The hardware cost is relatively clear, but the design cost is more complex. It includesthe salaries of design engineers, costs of EDA and other development tools, equipment costs, site costs, etc., and a significant portion is intellectual property costs, which vary greatly between different companies. Currently, the earlier costs are at a stable level, with little difference among companies, but the design cost of chips varies significantly due to intellectual property costs. For instance, MediaTek has to pay Qualcomm a huge amount in patent licensing fees, resulting in much higher costs compared to Qualcomm.
The internationally common chip pricing strategy is the 8:20 pricing method, meaning that with a hardware cost of 8, the price is set at 20. Intel generally uses an 8:35 pricing strategy, and AMD has historically reached an 8:50 ratio. A chip priced using the 8:20 strategy can be priced at $305 when the production volume is 100,000; $75 when the production volume is 1 million; and $52.5 when the production volume is 10 million. Thus, it is evident that to reduce chip prices, production volume is crucial. For example, if chips are produced in hundreds of millions, like Apple’s chips, even if the mask cost is as high as $1 billion, the cost allocated to each chip would only be $10. However, if the production volume is only 1 million, the mask cost per chip would soar to $1,000, which is clearly uncompetitive.
Newer processes can lead to lower chip prices and thus stronger market competitiveness, which is why giants like Apple and Qualcomm use TSMC and Samsung’s most advanced and expensive process technologies and still make huge profits; this also explains why IC design has a winner-takes-all characteristic; and this is also why domestic chip design companies are facing increasingly difficult paths.
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