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1. Introduction to the MIPI Protocol

MIPI (Mobile Industry Processor Interface) is an abbreviation of Mobile Industry Processor Interface. MIPI is an open standard established by the MIPI Alliance for mobile application processors. It defines a series of internal interface standards for mobile phones, such as the camera interface CSI and the display interface DSI. Among them, CSI (Camera Serial Interface) is the interface standard specified by the Camera working group under the MIPI Alliance. CSI-2 is the MIPI CSI second version, mainly consisting of application layer, protocol layer, and physical layer, supporting a maximum of 4-channel data transmission and a single-line transmission speed of up to 1Gb/s.

2. Layered Structure of MIPI CSI-2

CSI-2 can be divided into 5 layers, namely: application layer, packetization/depacketization layer, low-level protocol layer, channel management layer, and physical layer. The terminology involved in the layered structure is explained as follows:

Name	Explanation
Application Layer	Various algorithm modules that process raw image data
Packetization/Depacketization Layer	Responsible for slicing data into 8-bit data in a certain order.
Low-Level Protocol Layer	Adds header and footer to newly generated data, forming a data stream that meets protocol requirements.
Channel Management Layer	Manages read and write of generated data streams according to certain orders and requirements, outputting data streams.
Physical Layer	Generates the final signal waveform of MIPI.
Pixel Data	Data stream processed by the image module or the data path of raw images.
Transmission Data	Data sliced or added with headers and footers by the MIPI module.
Control Signal	Control data stream between modules
Sender	Includes the digital part of MIPI, adapter boards, etc., that implement MIPI signal source transmission.
Receiver	Includes adapter boards and commercial receiver modules responsible for parsing the received MIPI signal source.

In detail, the working sequence of the link is as follows:

• First, the original image data will undergo corresponding image processing in the application layer, including white balance, noise removal, color restoration, etc.

• The processed data enters the packetization layer for data segmentation and reassembly, and then is passed to the protocol layer. The protocol layer generates a header based on the data type, generates a checksum sequence for the footer based on the data content, and then combines the header, the data itself, and the footer to send to the channel management module.

• The channel management module allocates data to each channel reasonably according to the channel selection situation. After that, the data undergoes digital-to-analog conversion and enters the physical layer for transmission. The receiver, upon receiving the data from the physical layer, unpacks the original image data in the reverse order.

3. Physical Connection of MIPI CSI-2

Except for the ground wire, MIPI CSI-2 generally has 1 pair of I2C communication pins, 1 pair of MIPI differential clock pins, and 1~4 pairs of MIPI differential data signal pins. Explanation of various pins involved in CSI2:

Name	Explanation
DATA 1+ / DATA 1- MIPI	Second group of differential analog data signals generated by the protocol packetization
DATA 2+ / DATA 2- MIPI	First group of differential analog data signals generated by the protocol packetization
CLOCK+ / CLOCK- MIPI	Differential analog clock signal generated by the protocol packetization
SDA I2C	Data signal line
SCL I2C	Clock signal line

In typical applications, after the sender completes various processing of the image, data is packaged according to the protocol and then transmitted to the receiver through differential signal lines. The differential signal line generally includes a pair of clock differential lines and multiple pairs of data differential lines, the number of data differential signal lines depends on the amount of data to be transmitted. The larger the amount of data, the more pairs of data lines can more easily meet the link requirements. Generally, mobile phones with two million to five million pixels use two pairs of differential data lines, that is, two data channels. When the camera pixel further increases to eight million or even thirteen million, four data channels, that is, four pairs of differential data lines are generally used.

When interacting with external control signals, the I2C interface is used. The sender of MIPI uses I2C, and the control registers of the MIPI CSI-2 interface are connected to the slave end of I2C, so that external receiving devices can configure the internal registers of the MIPI sender through I2C, thereby changing the duration of the internal state machine of the MIPI CSI-2 interface and the number of channels when outputting the last data, or during debugging, reading these registers for corresponding checks to determine whether the sender is working properly, and analyzing whether the sender is in normal working condition through the phenomena of the receiver.

4. Working Modes of MIPI CSI2

MIPI signal transmission has two working modes: high-speed mode and low-power mode:

1. HS High-Speed Transmission Mode: High-speed data transmission, with signals being differential signals, the voltage range is 100mv-300mv, and the transmission speed range is 80-1000Mbps. In this mode, when the positive end of the differential line receives a 1.2V signal and the negative end receives a 0V signal, the receiver identifies it as 1, and vice versa as 0.

2. LP Low-Power Mode: Used for transmitting control commands, asynchronous transmission, with signal lines being single-ended, the voltage range is 0-1.2V, and there is no clock line; the clock is derived from the two data lines through XOR, with a speed of only 10Mbps. In this mode, when the positive end receives 300mV and the negative end receives 100mV, the receiver identifies it as 1, and vice versa as 0.

5. MIPI Transmission Timing

The transmission timing of MIPI is as follows, and the corresponding timing needs to meet the specification requirements; otherwise, there may be issues with recognizing MIPI signals. Typically, adjustments can be made by modifying settle time(40-85) and trail time(24~39):Clock and data reflect differential, that is, low bits come out first, hence it is represented this way, the differential signal P high N low represents 1, P low N high represents 0. Now you have a bit of an idea about MIPI. Let me show you her photo, I guarantee you will like it. What does MIPI output look like? MIPI’s beautified photo

• Frame header identifier, frame tail identifier (generated by vsync rising and falling edges respectively)

• Line header identifier, line tail identifier (generated by hsync rising and falling edges respectively)

• Effective data long packet. Contains line identifiers, so the line_sync short packet can be omitted

Compared to parallel transmission, it is to multiplex the vsync, hsync, and data in the same channel. In short, if it can be solved by software, do not touch the hardware, if it can be done manually, do not just talk. Life philosophy. What? Don’t look at photos that have been edited! Okay, here’s an unedited photo. Isn’t it beautiful? And mipi signals conform to its communication protocol, which stipulates that its starting voltage is between 1.1~1.3V, etc., as shown in the following figure (I am relatively lazy, if you don’t agree, come and argue). This is its electrical requirement. Then on the software side, as shown in the following figure: MIPI data long packet content

Term	Explanation
Byte(byte)	The basic unit of transmission, each byte contains 8 bits(bit)
Sync byte	Used to synchronize the start of data, informing that the following is valid data
DATA TYPE	What format of data is being transmitted in this packet YUV422(1E)/RAW8(2A)/RAW10(2B)
WC(16bits)	The number of bytes in PAYLOAD (i.e., how many bytes are in one row of the output window, which is also the number of columns. Note that raw10 is 1.25 times the number of columns, and raw12 is 1.5 times the number of columns)
ECC	Checks whether there is an error in datatype and wc
Payload	image data
CSC	Checks the transmission of PAYLOAD data

6. MIPI CSI2 Data Packet Format

MIPI CSI2 is a byte-oriented, packet-based protocol; it supports the transmission of arbitrary size data through short and long packet formats. Each packet is separated by the EOT-LPS-SOT sequence, as shown in the figure of MIPI CSI2 data packets.

LLP packets have two types: long packets and short packets. The transmission of each packet starts with SoT (start of transmission) and ends with EoT (end of transmission), with the gap in between being LPS (Low Power State).

6.1 Long Packet Format of MIPI CSI2

The long packet of MIPI CSI2 is mainly composed of a header, data packet, and footer. The header can be subdivided into: data identifier (data identifier), data packet size (word count), and error checking code (ECC). The data format of the long packet of MIPI CSI2 is shown in the figure. Among them,

• The data identifier size is 1 byte, containing the virtual data channel number [7:6] and data type [5:0].

• The data packet size is 2 bytes, its content is the length of the data being transmitted, in “words”.

• The error checking code size is 1 byte, responsible for checking and correcting errors during data packet transmission.

• The data packet can transmit a size of 0~65535 bytes.

• The footer size is 2 bytes, which checks the data load.

6.2 Short Packet Format of MIPI CSI2

Compared to long packets, short packets do not have data packets and footers. The data identifier DI’s data type is between 0x00 and 0x0F. The WC field is the data field of the short packet, which can be defined by the user. ECC is the checksum, which can correct 1-bit errors and check 2-bit errors, as shown in the figure.

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