MIPI is the most mainstream video transmission interface specification in the mobile field, and currently the most widely used are the MIPI DPHY and MIPI CPHY protocol families (there is also MIPI MPHY, which belongs to the high-speed Serdes category and is not as widely used). Among these, CSI-2 is mainly used for image input (usually connected to sensors), and DSI-2 is mainly used for image output (usually output to displays).
This article mainly takes CSI-2 as an example for detailed explanation, and DSI-2 is similar, so the same reasoning can be applied.
1 Interface Protocol Comparison
For detailed physical layer protocols of MIPI DPHY and MIPI CPHY, and the CSI-2/DSI-2 protocols, we can download the official English version for detailed reading; here we mainly discuss the key points.
1.1 Physical Layer
Starting with a diagram (see Figure 1), the content is substantial, and the differences between MIPI CPHY and DPHY physical layers are all in this diagram.
Figure 1 MIPI DPHY and CPHY Physical Layer Comparison Diagram
From Figure 1, we can see that the most intuitive difference is that DPHY is a source-synchronous system with a dedicated synchronization clock channel, while CPHY does not have a synchronization clock; the clock is embedded in the data. The obvious purpose of embedding the clock is to increase bandwidth, which will definitely involve encoding, and the physical layer structure will be completely different. Just from the line perspective, CPHY is a three-line system A/B/C.
The physical layer of MIPI DPHY is well understood; it has a pair of clocks, several pairs of data, and the receiving end samples data based on the clock edge, finding the 0xB8 synchronization header. Once the physical layer implementation is complete, it is done. However, MIPI CPHY is different because it does not transmit the clock. To receive CPHY data, the clock must be restored first, and then the restored clock is used to sample the data and find the synchronization header. Finally, data decoding is needed to recover the initially sent content (the sending process is the reverse).
So, how does the CPHY physical layer achieve the key step of embedding the clock? Please refer to Figures 2 and 3.
Figure 2 CPHY Line State Change Diagram
Figure 3 CPHY Interface Equivalent Circuit Diagram
Combining Figures 2 and 3, the CPHY physical link (A/B/C lines) transmits different levels, and through the level operations of A-B, B-C, and C-A, we recover +x, -x, +y, -y, +z, -z six different line states. By analyzing the rotation direction, phase, and polarity of the front and back line states, we recover the encoded symbols. Then, through 7 consecutive symbols, we decode the 16-bit data. The entire process is shown in Figure 4.
Figure 4 Data Recovery Process Diagram
Why choose this more complex physical layer than DPHY? Everything is to enhance bandwidth. From Figure 2, it can be seen that there can be 5 different variations of a certain line state, so each symbol can encode data as log2(5) = 2.3219, and the theoretical bandwidth is 2.3219 times that of DPHY. Each 16-bit data is encoded into 7 symbols, making the bandwidth advantage obvious.
1.2 CSI-2 Layer
The CSI-2 layers of MIPI CPHY and MIPI DPHY are roughly the same, with the following detailed differences:
(1) DPHY organizes data by Byte; CPHY organizes data by 16-bit Word;
(2) The short frame and long frame header information and data organization method of DPHY are the same; CPHY has a fixed header information of 6×16-bit for each channel (short frame information), as shown in Figure 5.
Figure 5 CPHY CSI-2 Data Organization
Therefore, the unpacking logic of CSI-2 cannot be completely shared.
2 FPGA Implementation
The MIPI interface levels are quite special, with the LP mode at 1.2V LVCMOS level, DPHY at HS mode being SLVS-400 level, and CPHY needing to perform level subtraction operations at HS mode.
2.1 Hardware Circuit
Currently, the FPGA that directly supports MIPI DPHY mainly includes Xilinx UltraScale+ series (1.5Gbps/Lane Max), Lattice Crosslink (1.5Gbps/Lane Max), and Lattice Crosslink NX (2.5Gbps/lane Max). Other FPGA models need to add additional level conversion circuits to convert the signals to LVDS.
(1) For DPHY, below 800Mbps/lane rate, a resistor network is sufficient; for high rates, a dedicated level conversion chip should be used, such as MC20901, LT89101L, etc.;
(2) For CPHY, since level subtraction is required, a dedicated comparator (or Repeater) can be used, and the result is output in LVDS level.
2.2 Logic Implementation
The differences in logic implementation mainly lie in the physical layer, where CPHY and DPHY are completely different.
2.2.1 MIPI DPHY
MIPI DPHY is a source-synchronous system. After converting to LVDS level, it is a general ISERDES logic. There are two considerations for the clock scheme:
The first option: use PLL, MMCM, or DLL. This scheme has a high requirement for the locking time of the PLL, usually requiring us-level to ensure normal locking in a clock discontinuous mode. Of course, devices with dedicated DPHY logic have dedicated PLL circuit implementations. The advantage of this scheme is that it is not easily affected by clock glitches, making reception more stable.
The second option: based on the source-synchronous clock, use a dedicated clock buffer to divide (such as the BUFR of Xilinx 7 series). This scheme can adapt to any rate without needing to preset the rate to configure the phase-locked loop circuit. The downside is that it is susceptible to clock glitches, resulting in a slightly higher error rate.
2.2.2 MIPI CPHY
The difficulty of MIPI CPHY lies in clock recovery. In FPGA systems, there are no dedicated clock recovery circuits (CDR) for MIPI CPHY, so it is necessary to fully utilize CPHY’s line state encoding equalization and FPGA programmable delay circuit characteristics to implement CDR. This scheme theoretically requires the internal delay logic of the FPGA to be as precise as possible, and the LUT clock performance to be as high as possible, which will minimize clock recovery errors and jitter. After clock recovery is completed, the line state decoding, symbol decoding, and data recovery processes are shown in Figure 4.
In summary, MIPI CPHY has doubled the bandwidth compared to MIPI DPHY while reducing the number of lines, becoming increasingly popular in high-speed large-area sensors and high-resolution, high-refresh mobile devices OLED applications.
2.2.3 Resource Occupation
Panda has verified the MIPI DPHY+CPHY receiving IP on Xilinx Kintex-7 series FPGA, occupying resources of SliceLUTs 2352 and Slice Registers 3401. This scheme can also be implemented on domestic FPGAs such as Unisoc Tongchuang and Haoyun.
Figure 5 MIPI DPHY+CPHY Vivado Project Diagram
Welcome to join QQ group or WeChat public account for related technical discussions.
