MIPI (Mobile Industry Processor Interface) is an industry specification designed for mobile devices such as smartphones, tablets, laptops, and hybrid devices. The common physical (PHY) layers are MIPI D-PHY and C-PHY.
MIPI D-PHY: It is more commonly used for the cameras and displays of smartphones due to its flexibility, high speed, low power consumption, and low cost. It provides a physical layer definition for DSI (Display Serial Interface) and CSI (Camera Serial Interface), using a differential clock and 1-4 pairs of differential data lines to transmit data.
MIPI C-PHY: C-PHY does not have a synchronized clock; instead, the clock is embedded within the data, achieving high throughput performance through bandwidth-limited channels, such as connecting displays and cameras to application processors. It provides PHY for the MIPI Camera Serial Interface (MIPI CSI-2) and MIPI Display Interface (MIPI DSI-2) ecosystem, helping designers extend their implementations to support various higher resolution image sensors and displays.
1. PCB Layout Requirements for MIPI Interface
1. Keep away from interference sources to prevent other signals from interfering with the transmission rate and signal quality.
2. All display interfaces (regardless of whether they are in connector or FPC form) should be placed as close to the board edge as possible for easy insertion and removal.
3. The distance between the main chip and the display interface should not be too far apart; minimize the wiring distance and route according to high-speed signal guidelines.
4. If the PCB has structural requirements, placement should strictly follow the structure.
2. PCB Routing Requirements for MIPI Interface
1. Reference Layer: To suppress electromagnetic radiation, the differential lines of MIPI should be routed as close as possible to the GND plane, ensuring that the routing does not cross splits; otherwise, it may cause discontinuity in differential line impedance and increase external noise affecting the differential lines. If routed on the surface layer, ground shielding or increased spacing from other signals should be applied.
2. Ground Shielding: MIPI routing can be grouped with ground shielding, and GND grounding vias should be placed every 150 mil. If space allows, single-group grounding can be applied.
3. Minimize the number of vias for layer changes in MIPI signal differential lines, as vias can cause impedance discontinuities. If vias are needed for routing, ensure consistency in differential vias and arrange a return ground via close to the via location for signal return.
4. Interference Principles: MIPI signal lines should be kept away from other high-speed signals (such as parallel data lines, clock lines, etc.), and should be especially distanced from interference sources like switch power supplies.
The PCB design routing considerations for MIPI-DPHY interface are shown in Table 1 below:
Table 1: PCB Design Routing Considerations for MIPI-DPHY Interface
The PCB design routing considerations for MIPI-CPHY interface are shown in Table 7-8 below:
Table 2: PCB Design Routing Considerations for MIPI-CPHY Interface
It is also recommended to add ground vias in the following positions in the BGA area, as shown in Figure 1:
Figure 1: Addition of Ground Vias Under the BGA Area
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