Understanding MIPI C-PHY and D-PHY Subsystems

Weighing pros and cons, challenges and adoption

Ashraf Takla, Mixel, Inc., CEO

Source: Mixel

(First published in April 2018. Updated in March 2022.)

MIPI® C-PHYSM was introduced in October 2014, creating excitement and concern. How does this new C-PHY compare to MIPI D-PHYSM and M-PHY®? What are the differences with C-PHY, and is it compatible enough with D-PHY to coexist in a mixed subsystem?

Years later, the answers are clear.

This article will elucidate these answers, providing a high-level overview of D-PHY and C-PHY architectures, highlighting their similarities and differences, identifying the advantages and disadvantages of each PHY, and offering insights into some of the challenges encountered when implementing C-PHY. Finally, we will explore Mixel®’s innovative implementation of C-PHY/D-PHY combo IP, silicon results from multiple sources, cover use cases, and examine the market adoption of C-PHY/D-PHY combo solutions.

Let’s first take a closer look at D-PHY, which has been around since 2009, thus gaining better understanding and widespread application. D-PHY is a simple source-synchronous PHY, using one clock channel and a varying number of data channels. The block diagram of D-PHY with four data channels is shown in Figure 1, with details of each channel shown in Figure 2. With D-PHY being on the market for nearly a decade, there is a wealth of literature covering its unique features and usage (1).

Figure 1: D-PHY Block Diagram with Four Data Channels

Figure 2: Block Diagram of D-PHY Data Channel

In contrast, C-PHY is a newer and more complex PHY. It operates on three signals, combining clock embedded within the data, eliminating the need for a separate clock channel. The block diagram of C-PHY is shown in Figure 3.

Figure 3: C-PHY Block Diagram

Table 1 compares D-PHY and C-PHY.

Table 1: C-PHY vs. D-PHY Parameters Comparison

Notes:

(1) Four data D-PHY channels compared to three MIPI C-PHY tri-channels

(2) Higher bandwidth from encoding

C-PHY uses encoded data to package 16/7≈2.28 bits/symbol, while D-PHY does not use any encoding. As a result, C-PHY can achieve higher data rates compared to D-PHY while operating at the same transition or symbol rate.

At first glance, the workings of C-PHY, as well as the potential C-PHY/D-PHY combo, seem mysterious. C-PHY signaling is multi-level, but its receivers do not need to detect differences between levels! How is that? Why do C-PHY and D-PHY have distinct differences, yet they can not only coexist but effectively combine into one IP? D-PHY uses differential signaling, while C-PHY uses triple signaling. Can they work together? How to effectively implement the C-PHY/D-PHY combo using all of D-PHY building blocks without any duplication? How is the ratio of 16/7 derived for the number of data bits per symbol? There are so many questions to ponder!

Let’s attempt to answer these questions, first by trying to unravel the mystery of C-PHY. This is not an easy task. Below in Figure 4, we provide a quick overview of C-PHY. The block diagram in Figure 4(a) shows how a tri-channel C-PHY TX and RX are connected. Figure 4(b) illustrates the different sub-blocks in the C-PHY subsystem, i.e., mapping, parallel/serial functions, encoding, and channels. Figure 4(c) provides a more detailed picture of the interaction between TX and RX, while Figure 4(d) explains the signaling levels of C-PHY.

Figure 4: C-PHY (a) TX and RX Connection, (b) Different Functions in C-PHY Subsystem, (c) Detailed TX and RX Interaction, (d) C-PHY Signaling Levels

A C-PHY lane consists of A, B, and C, as shown in the above Figure 4(c). The C-PHY receiver consists of three differential RXs, each looking at two of the three signals differentially, i.e., (A-B), (B-C), and (C-A).

The C-PHY encoder ensures (i) there is at least one edge/transitions per symbol, (ii) all three RX differential inputs are non-zero, and (iii) the common mode of all three signals is constant. The aforementioned (ii) and (iii) are achieved by limiting the TX signal combinations within any single Unit Interval (UI) to high, mid, low, and keeping the voltage levels of each signal among the three distinct. The three TX signal levels combination that meets the above constraints (i) can yield six different signal level combinations (line states). The number of line states, 6, is the permutation of three TX signal levels, 3!. Furthermore, the C-PHY encoder flips, rotates, and polarity encodes based on state transitions dictated by the encoder rules.

To ensure at least one edge per symbol, the above item (i), C-PHY must transition between different line states when moving from one symbol to the next, and cannot maintain the same line state in two consecutive symbols. Due to this restriction, there are five different unique transitions among the six line states. This means the encoded data has five different possibilities, i.e., five possible states per symbol, making C-PHY a quinary system or quaternary system. This is how we move between binary and quaternary systems. This is why the C-PHY mapper is necessary. Now we are using a quinary system, and the maximum theoretical number of bits/symbol is log2(5)=2.3219. The mapping function is constructed to keep the mapping rate as close as possible without exceeding that theoretical limit. Additionally, the mapper must map between two integers. The choice of ratio 16/7≈2.28 is made to achieve the above constraints.

Another way to describe this is that the mapper needs to map 16 binary bits to a certain number of C-PHY symbols, but how do we determine how many symbols (S) to map to? There are 2^16 combinations on the parallel interface, and the combinations at the mapper output are 5^S => 2^16, thus S = 7.

Figure 5: Overview of C-PHY Encoding and Mapping Functions

To understand why the C-PHY receiver only needs to detect the polarity of the input signals and not the amplitude of multi-level signaling, we only need to remember that there is no data embedded in the signal amplitude. Multi-level signaling is used solely to increase the possible number of transitions and ensure that there is at least one transition per symbol.

A comparative analogy between the performance of C-PHY and D-PHY is when they support a total data rate of 4.0Gbps and operate at similar transition rates. For D-PHY, this can be achieved by using a four-channel D-PHY, utilizing 10 data lines, with each channel operating at 1.0Gbps/channel. To achieve the same or lower transition rate total data rate as C-PHY, we could use a dual-channel C-PHY with 6 lines operating at 0.875Gsps, which is lower than D-PHY’s 1.0Gsps. In this case, the total data rate of C-PHY is 2 * 0.875 * 16/7 = 4Gbps. This comparison is illustrated in Figure 6 below.

Figure 6: Comparison between D-PHY and C-PHY Supporting 4Gbps Aggregate Data Rate and Using Same Transition Rate

Based on this comparison, C-PHY has fewer wires (up to 40% reduction), lower switching rates/channel (12.5% reduction), lower power consumption (approximately 20-50% reduction), fewer channels, hence smaller area for the same Gbps, and no clock channel consumption.

Therefore, when comparing C-PHY and D-PHY at the same total data rate, C-PHY has many advantages; fewer pins and solder balls (due to higher performance per pin), flexibility as each C-PHY channel is independent with embedded clock allowing one channel to borrow from another link while coexisting with MIPI D-PHY on the same pins. C-PHY also allows for lower power in higher data rate applications. Furthermore, the embedded clock channel of C-PHY can allocate any channel on the application processor to any link and eliminates clock spurious emissions, which is particularly important in multi-band wireless devices.

The embedded control code of C-PHY also effectively supports emerging functionalities such as fast bus turnaround (BTA) operations, low latency (LRTE) for time-sensitive links, and backup low power mode (ALP), which will achieve longer transmission distances by eliminating single-ended LP mode, thus reducing area. Finally, the lower switching rate of C-PHY typically simplifies manufacturing and reduces costs for low-cost products, such as low-end cameras.

Now that we have understood the various attributes of C-PHY and D-PHY, we can enumerate some advantages of the C-PHY and D-PHY combo. These include the ability to share serial interface pins, reuse LP (low power) modes, share common blocks, thus reducing area, lowering power/Gbps, smooth transition between MIPI D-PHY and MIPI C-PHY, leveraging MIPI C-PHY’s power/performance/area (PPA) improvements while maintaining compatibility with MIPI D-PHY.

Mixel’s implementation of C-PHY/D-PHY combo IP is unique. All D-PHY blocks are repurposed for C-PHY operation (HS-TX, HS-RX, SER, DESER, LP-TX, LP-RX, and LP-CD), minimizing area overhead to support C-PHY. While all blocks are reused, the encoder, decoder, CDR, mapper, and demapper are additional modules required for C-PHY functionality. The block diagram of Mixel’s implementation is shown in Figure 7.

Figure 7: C-PHY/D-PHY Combo IP Block Diagram

Combo C-PHY/D-PHY has been implemented by Mixel in many different nodes and foundries. In fact, Mixel’s MIPI IP has been silicon-validated across 12 different nodes and 8 different foundries.

Below we showcase the test setups and chip evaluations for C-PHY and D-PHY transmitters.

Figure 8: MIPI C-PHY Transmitter Test Setup

1.5Gsps

2.5Gsps

Figure 9: Chip Results: TX MIPI C-PHY – Eye Diagram (Mixel)

1.05Gsps @ std channel

2.5Gsps @ short channel

2.5Gsps @ std channel

Figure 10: Chip Results: TX MIPI C-PHY – Eye Diagram (Qualcomm)

3.5Gsps @ standard channel

1.5Gbps 2.5Gbps

Figure 12: Chip Results: TX MIPI D-PHY – Eye Diagram (Mixel)

2.5Gbps @ short channel

4.5Gbps @ short channel

Figure 13: Chip Results: TX MIPI D-PHY – Eye Diagram (Qualcomm)

Below we showcase the test setups and silicon evaluations for C-PHY and D-PHY receivers.

Figure 14: Chip Results: RX MIPI C-PHY – Electrical (Qualcomm)

Figure 15: Chip Results: RX MIPI C-PHY – Link (Qualcomm)

Figure 16: Use Case Example: Camera Invocation

Figure 17: Use Case Example: Display Invocation

Now, let’s take a look at the power, performance, and area of different use cases in current display and camera applications. These are shown in Table 3.

When comparing D-PHY and C-PHY/D-PHY combo at the same data rates, the area increase is minimal. The normalized power of only the C-PHY module is quite comparable when compared at the same Gbps. At the same transition rates, C-PHY has a clear advantage over D-PHY, achieving higher data rates.

However, the power increment of combo PHY can be canceled by enabling various design options in C-PHY mode configurations (not shown here).

Table 3: PPA of Different Use-Cases for Display Applications

Table 4: PPA of Different Use-Cases for Camera Applications

Notes:

1.Combo PHY area increment < 10%

2.Combo PHY can cover a wide range of resolutions: 80Mbps – 10Gbps – 17.1Gbps – 18Gbps – 23.94Gbps

3.MIPI C-PHY mode: due to lower frequency/smaller bias/fewer channels, power consumption is approximately 10-30% lower than DPHY mode

4.Provided by Qualcomm

C-PHY/D-PHY combo has been widely adopted across multiple use cases, many different vendors, and various types of products, including cameras (Sony, OVT, and others), displays (interoperability tests completed with most major DDIC companies). The ecosystem is supported by extensive participation, including IP (Mixel), AP/SOC (Snapdragon, etc.), test equipment (Keysight, Tektronix, Introspect, The Moving Pixel Company), and common mode filters (Murata, Panasonic, TDK).

However, the higher performance of C-PHY does not come without challenges; it brings some challenges, including unique CDRs programmed for different data rate ranges, multi-level signaling transmission introducing encoding jitter, and the unique trio-based signaling that complicates PCB design.

In conclusion, MIPI C-PHY is a more complex, powerful, and efficient PHY, and the C-PHY/D-PHY combo is even more so. Mixel has created and silicon-validated a dual-mode MIPI D-PHY/MIPI C-PHY, achieving a smooth transition between the two PHYs. Mixel’s dual-mode MIPI D-PHY/MIPI C-PHY shares all common modules, thus reducing area and lowering power/Gbps. It benefits from MIPI C-PHY PPA improvements while maintaining compatibility with MIPI D-PHY and using the same serial interface pins. Moreover, the MIPI C-PHY/MIPI D-PHY combo has been silicon-validated across multiple nodes and foundries and has been integrated by many Tier 1 SOC, sensor, and display vendors into several end products. Since its debut, we have seen the MIPI C-PHY/MIPI D-PHY combo increasingly attractive in various applications for cameras and displays, including mobile and mobile-adjacent applications such as VR/AR/MR, automotive, IoT, and more.