Summary of SOC Chip Leakage Current Failure Analysis Case Study [Part B: Layout Manager’s Statement]

In the previous article “Summary of SOC Chip Leakage Current Failure Analysis Case Study [Part A: Analog Manager’s Statement],” the Analog Manager pointed out that the reason for the SOC failure was the addition of digital buffers to drive analog level signals during the digital layout. So how will the Layout Manager respond? What opinions will he express, and what statements will he make? Let’s take a look at his insights. The content is as follows.Parameters related to the analog-digital interface signals and the missing IO lib files have been a long-standing vulnerability for us, and the feasibility of specific implementations may need to be considered by everyone. For similar issues in this and previous projects, the following improvements can be made: top-level designers should standardize documentation or annotate in the circuit.For top-level designs driven by digital processes:Signals coming from the analog block and I/O are defined into four categories: power/ground, analog, signal, and clock. 1. P/G: For non-*VDD* and *VSS* signals, such as VMAX, VPP, etc., please specify the current capability requirements. This needs to be planned during the power planning phase.2. Analog: When designing analog circuits, please consider two parameters: transition and capacitance. If these are not considered internally, please specify their parameter attributes, allowing for processing in the digital flow. Conversely, if no processing is done on the digital side and only wiring is performed, please specify any special requirements for the wiring.3. Signal: Logic level signals corresponding to digital power, 0 and 1. If not, please perform level shifting. For signals not corresponding to digital power, please handle them as analog signals.4. Clock: Signals of this type will have their attributes defined by the digital front-end designers, including important parameters. Currently, all are included, and no further description is needed here. It should be noted that some analog designers may consider signals with clock characteristics as not being clocks; please annotate these in the analog layout or digital design and layout to consider whether related processing is needed. For individual signals with rise and fall time requirements, please specify; both digital SDC and layout can meet the constraints; if not specified, they will be treated according to general digital constraints.For the corresponding handling of the above signal types, analog circuit designers, digital circuit designers, and back-end layout and design must all check and confirm.Additionally, regarding the final LVS netlist issue, it actually conforms to the top-level being driven by digital; theoretically, the only party that can make mistakes is the digital circuit side. If problems arise, it indicates that the documentation is not standardized or that the documentation instructions were not followed. For the current solution, please ensure documentation is standardized, the top-level circuit is correct, and the digital design references the circuit. All naming in the documentation must be consistent with the circuit; if inconsistent, please annotate. Mutual checks between the top-level designers of analog and digital circuits can greatly reduce the probability of errors.In previous projects like AAA and BBB series, some adopted top-level designs managed by the analog side, theoretically making the only possible error source the analog circuit side.Regardless of the process, it is essential to ensure the correctness of the final designer. For top-level designers, the blocks provided by the lower levels are black boxes; the more detailed the interface pin parameter descriptions, the lower the probability of errors in the intermediate links.Moreover, we actually have very little or no time reserved for various checks before tapeout, so in the future, please ensure that circuit designers thoroughly check the final layout, as some errors cannot be detected by DRC or LVS checks.The above is the summary shared by the Layout Manager.Do you think the Layout Manager’s statements are reasonable? Do you agree?If you agree, please like and save.If you disagree, feel free to leave comments in the discussion area below!