This material is sourced from company announcements, related news, publicly available research reports, and social media networks. It does not constitute investment advice regarding the industries and stocks mentioned in the text. If there are any infringements or violations of information disclosure, please contact us for removal.Q: What are the main projects and progress of ASIC custom chips at ByteDance?A: The company has three core projects in the ASIC custom chip field with ByteDance, each with clear progress and positioning. The first is the VPU chip project, expected to enter mass production in April 2026. The company is focusing on products for this timeline, with the core goal of establishing a long-term partnership with ByteDance through first-mover advantage. However, the current market for VPU products is highly competitive, with relatively low profit margins, while other manufacturers are focusing on products slated for mass production in 2027, creating a differentiated competitive landscape. The second is the NPU chip project, expected to enter mass production in August 2026. ByteDance has invested $250 million in the R&D phase, with this revenue primarily belonging to the company. However, due to significant initial R&D investments, profitability during this phase is low. In the mass production phase, ByteDance plans to invest $400 million, expecting to produce 300,000 chips in 2026. During this phase, about half of the revenue will go to the company, with the remainder covering packaging, testing, and other costs, and the chip production costs paid directly to Samsung by ByteDance. Currently, ByteDance, the company, and Samsung have established deep cooperation and formulated a five-year plan, with Samsung also planning to attempt to shift some production capacity domestically to further optimize the supply chain. ByteDance’s NPU products are likely to adopt an annual iteration rhythm and are expected to maintain long-term cooperation with Samsung. Since the first-generation products are designed by the company and establish standards, subsequent generations are likely to continue this standard, thus the company is expected to maintain a high market share in future ByteDance NPU projects. The third is the VR glasses project, which began in 2023 and is currently in the iteration phase, with current revenue below 100 million RMB. Mass production is expected by the end of 2026 or 2027, with the company only responsible for the chip design phase, later obtaining revenue through IP licensing without participating in the mass production phase. Based on expected production of hundreds of thousands of units, if the IP licensing model is adopted, each chip could bring the company 10-20 RMB in revenue; if the chip licensing model is adopted, revenue per chip could reach several tens of RMB, providing a flexible revenue model with long-term profit potential.Q: What are the main projects of ASIC custom chips at Alibaba?A: The company collaborates with Alibaba in the ASIC custom chip field across multiple scenarios, with three core projects. The first is the Shadow Cloud project, which primarily provides cloud services for non-developer groups. Since cloud services require handling a large number of graphics rendering tasks, the demand for resource interfaces is extremely high, thus essentially requiring a high-performance VPU chip to support it. However, this project is managed by Alibaba’s Damo Academy, and the company is not the main party, only undertaking part of the R&D and design work, with a relatively minor role in the collaboration.The second is the cryptocurrency-related chip project, which provides customized ASIC chip solutions to meet the specific needs of cryptocurrency computation scenarios, assisting Alibaba in its technological layout and business expansion in this field.The third is the Orca Entertainment project, focusing on internet entertainment scenarios, providing dedicated ASIC chips for Orca Entertainment’s gaming and live streaming businesses to optimize computational efficiency and cost control. Currently, all three projects are progressing as planned, each with clear scenario positioning and division of labor.Q: What is the project situation of ASIC custom chips at Tencent and Amazon?A: The cooperation models and project focuses between the company and Tencent, as well as Amazon, show significant differences. In the collaboration with Tencent, the core model is IP licensing, where the company provides ASIC custom chip-related intellectual property rights to Tencent, which then conducts its own chip R&D or product applications based on these IPs. The company does not directly participate in the chip design and production phases, focusing on intellectual property output, making the model relatively asset-light. In contrast, the collaboration with Amazon is more substantial and long-term. Amazon signed a multi-hundred-million-dollar cooperation agreement with the company from late July to early August this year, covering the years 2025, 2026, and 2027, with the core R&D direction being NPU chips.However, it is important to note that Amazon’s overall investment in the large-scale computing field is significant, and the company only participates in certain aspects, mainly responsible for the customized design of NPU chips and related technical support, rather than undertaking all project R&D. The collaboration focuses on core chip aspects, complementing Amazon’s own technical system.Q: What are the main projects and progress of ASIC custom chips at BYD and Li Auto?A: In the automotive client sector, the company’s collaboration with BYD and Li Auto on ASIC custom chips focuses on intelligent driving scenarios, with clear project progress and division of labor. For BYD, the core project is the “Eye of God” intelligent driving chip, which is mainly applied in vehicle interconnection scenarios, specifically including the vehicle networking interaction function equipped with WiFi modules. The company is only responsible for the chip design phase in this project and does not participate in subsequent mass production. The project is progressing smoothly, and it is expected to be completed by the end of this year. After completion, based on BYD’s business needs, there may be further chip iteration cooperation, forming a long-term service relationship.For Li Auto, the collaboration project is also an intelligent driving chip, with Li Auto having invested 150 million in this project last year, and there may be additional investments by the end of this year.The company provides comprehensive support in the collaboration, including IP licensing, personnel outsourcing services, and chip design platform establishment, with all project-related intellectual property rights belonging to Li Auto. To better ensure project progress and adaptation needs, the company has specifically dispatched a team to Li Auto to conduct R&D work internally, deeply integrating into the client’s development process to ensure that chip design is highly compatible with Li Auto’s intelligent driving system.Q: What is the project progress with major mobile clients Xiaomi and VIVO?A: The company’s collaboration with these two major mobile clients covers multiple product lines, with clear project progress and future planning. In collaboration with Xiaomi, there are three core projects:First, the NPU IP licensing for the Xuanjie chip, where the company provides NPU-related intellectual property to support Xiaomi’s development and application of the Xuanjie chip;Second, the chip business for wearable devices such as watches and bands, which has currently generated over 100 million RMB in revenue. The core highlight is that the chip supports non-invasive blood pressure detection, significantly improving the accuracy of blood pressure detection through deep learning algorithms, enhancing product competitiveness;Third, the traditional home appliance chip business, covering chip supply for devices such as projectors, hair dryers, and toothbrushes, which can bring the company stable annual revenue of 100-200 million RMB, forming a diversified cooperation pattern.In collaboration with VIVO, the focus is on flagship NPU chips. The NPU chip used in the flagship model released by VIVO in March this year was designed by the company, and both parties have agreed to adopt an annual iteration rhythm to continuously optimize NPU performance to meet the upgrade needs of VIVO’s flagship models. Additionally, the company is also expanding its mobile client base, with brands like Realme and Coolpad in discussions, and it is expected to sign cooperation orders before the end of this year, further expanding market share in the mobile field.Q: What is the order trend for the fourth quarter and next year?A: From the order trend perspective, the company has clear support for both short-term and long-term order growth. In terms of fourth-quarter orders, based on the current cooperation progress with existing major clients, project advancement rhythm, and existing demand communication, it is expected that the new order volume in the fourth quarter will not be less than that of the third quarter, with order scale remaining stable. This is mainly due to the continuous advancement of existing projects and the steady release of customer demand, with no significant risk of quarterly decline. For next year’s orders, the main incremental source of new orders is clearly directed towards existing major clients. On one hand, existing major clients (such as ByteDance, Alibaba, Xiaomi, VIVO, etc.) have many projects in long-term cooperation cycles, which will enter iteration or expansion phases next year, bringing incremental orders. On the other hand, the company has established deep cooperative relationships with existing major clients, with strong trust foundations and technical compatibility, making clients more inclined to entrust new demands to the company rather than redeveloping new suppliers. Therefore, the certainty of order growth next year is high, with growth momentum concentrated in the core client group.Q: In the AI era, what are the main opportunities for the RISC-V architecture, and what measures is the company taking?A: In the AI era, the RISC-V architecture, with its unique advantages, presents two core opportunities. First, AI scenarios require a large number of ASIC chips to support efficient computation, and how to better adapt CPUs to the increasing number and rapid iteration of ASIC chips has become a key industry issue. The RISC-V architecture has significant advantages in this adaptability, enabling better coordination between CPUs and ASICs to enhance overall computational efficiency. Second, the RISC-V architecture itself adopts a modular design, which is more flexible and efficient than traditional architectures (such as x86, ARM) in allocating learning paths, data paths, and memory calls between general-purpose chips and dedicated chips, better adapting to the diverse computational needs in AI scenarios and reducing the collaboration costs between different types of chips. To seize these opportunities, the company has taken clear measures by acquiring RISC-V chip-related enterprises to fill its technical gaps in the RISC-V architecture field, preparing for future orders in this area. Currently, there is potential demand for CPU orders, and the acquisition actions are aimed at better meeting these needs and enhancing market competitiveness based on the RISC-V architecture in the AI era.Q: Why does Chiplet technology have particularly large development opportunities in the AI field, and what are its core advantages?A: Chiplet technology has significant development opportunities in the AI field due to its technical concept being highly compatible with the demands of the AI sector, possessing two key advantages. This technology was first proposed by automotive companies, with the core idea being to package different functional modules of a chip separately through “high cohesion and low coupling.” When a specific functional module needs to be upgraded, there is no need to redesign the entire large chip; only the corresponding chiplet for that module needs to be replaced or upgraded. For example, an automotive company may iterate the camera-related chiplet in one year and upgrade the temperature sensor chiplet the next year without needing to reconstruct the entire chip system. This characteristic perfectly adapts to the demands of the AI field, where chip design needs to quickly respond to the dynamic changes in different modal requirements. For instance, in early 2025, the rapid iteration of language models leads to a surge in demand for hardware modules related to language understanding; at this time, only the language processing chiplet needs to be upgraded. In mid-2025, if there is an explosion in demand for video modalities (such as video processing, text-to-video, image-to-video), the video processing chiplet can be specifically upgraded. Since the explosive points of AI training at different times are concentrated on specific modalities and change frequently, the “local upgrade” feature of Chiplet technology can significantly enhance chip iteration efficiency, avoiding the time waste caused by full chip reconstruction. At the same time, there is no need to redesign non-upgraded modules, greatly reducing R&D costs and minimizing resource waste. Therefore, in the context of the AI field’s dual pursuit of efficiency and cost, the development opportunities for Chiplet technology are particularly prominent.Q: Will Qualcomm’s recent acquisition of AlphaWeave affect the company’s cooperation with AlphaWeave? Does the company plan to acquire other similar SerDes chip projects?A: Qualcomm’s acquisition of AlphaWeave will not have a significant impact on the company’s cooperation with AlphaWeave. The core reason is that the cooperation model between the two parties (mainly based on IP licensing and agency) has not changed, and Qualcomm is unlikely to directly terminate existing business arrangements in the short term due to its own economic interests. The existing cooperation provides stable revenue sharing for Qualcomm, and a hasty termination would harm its short-term profits and disrupt the smooth transition of AlphaWeave’s business. According to the communication results between the company, Qualcomm, and AlphaWeave, the company will still maintain its position as the general agent for AlphaWeave series chips in the Chinese market for the next three to four years, allowing for normal agency and cooperation business to continue, ensuring clear stability in cooperation. Regarding the acquisition of other similar SerDes chip projects, the company has developed preliminary plans and strategies for potential targets, but there will be no substantial actions in the short term (within the next six months) unless there are significant changes in AlphaWeave’s business (such as technical route adjustments or significant market share declines) that prevent the existing cooperation from meeting the company’s needs. The current focus remains on maintaining the existing cooperation with AlphaWeave.Q: After providing chip design services to clients, do most clients choose to have the company handle subsequent mass production? What factors do clients primarily consider in making this decision?A: After providing chip design services, not all clients choose to have the company handle subsequent mass production. Clients’ decisions are mainly based on their strategic needs, cost control, and supply chain management capabilities, showing significant differentiation. One type of client, such as Xiaomi, places more emphasis on controlling the entire supply chain and prefers to integrate the chip mass production phase into its own supply chain system to avoid the inefficiencies or uncontrollable costs that may arise from excessive involvement of external suppliers. Therefore, this type of client usually connects with mass production manufacturers (such as wafer fabs and packaging/testing factories) after the company completes the design, leading the subsequent mass production process. Another type of client, such as ByteDance, focuses more on improving yield rates and shortening time cycles in the mass production phase. The company has rich experience in overseas supply chain cooperation (such as with Samsung) and mass production process optimization, which can help ByteDance quickly improve chip yield rates and shorten mass production cycles. Therefore, this type of client tends to prefer the company to handle subsequent mass production, leveraging the company’s resources and technical advantages to advance the project. Additionally, some clients consider bargaining power and do not want a single party (such as the company) to dominate both the design and mass production phases, fearing that their bargaining power may weaken in subsequent collaborations. Thus, they may choose to lead mass production themselves, introducing multiple suppliers to create competition and safeguard their bargaining power.Q: What is the proportion of self-owned IP versus purchased IP in the chip products designed for clients? Is this proportion calculated based on value or quantity?A: The proportion of self-owned IP to purchased IP in the company’s chip designs is not fixed and varies significantly depending on the project type (chip functionality, application scenarios). All proportion data is calculated based on value (i.e., the technical value and licensing fees of the IP), rather than quantity (such as the number of IP modules). Specifically, in NPU projects, the company’s self-owned IP accounts for the highest proportion, about 70%, because the company has laid out early in the NPU field and accumulated a large amount of core intellectual property, covering the main functional modules of NPU chips with low reliance on purchased IP. In VPU projects, the self-owned IP proportion is about 50%, as VPU chips involve some special functional modules (such as high-end graphics rendering), where the company’s IP accumulation is relatively insufficient, necessitating the purchase of some core IP for supplementation. In CPU projects, the self-owned IP proportion is usually below 50%, as CPU architectures are complex and have high technical barriers, with established third-party IP suppliers (such as ARM) in the industry. To ensure CPU performance and compatibility, the company purchases a significant amount of core IP (such as instruction sets and arithmetic unit IP), with self-owned IP mainly used to adapt to clients’ customized needs, resulting in a relatively low proportion.Q: What is the current proportion of one-time licensing fees versus mass production profit-sharing in the company’s IP licensing revenue? How do these two models work together?A: Taking the IP licensing revenue structure for 2025 as an example, one-time licensing fees account for about 60%, while the mass production profit-sharing model accounts for about 40%. These two models flexibly collaborate based on project progress and client needs, forming a complementary revenue structure. From an operational logic perspective, one-time licensing fees are mainly collected during the chip design phase. When clients initiate chip R&D projects, the company licenses relevant IP for the design phase, collecting a fixed licensing fee at once. This model can provide stable cash flow for the company in the early stages of the project, covering some of the initial R&D investments. The mass production profit-sharing model, on the other hand, starts when the chip enters the mass production phase. The company charges profit-sharing fees based on the actual mass production quantity of the client’s chips, with larger production scales leading to higher profit-sharing income. This model allows the company to share the long-term revenue of clients’ products, especially when clients’ product sales explode, bringing significant revenue increments. In actual cooperation, the proportions of these two models can be adjusted based on client needs: for example, some clients may wish to reduce initial investment pressure, and the company can appropriately lower the proportion of one-time licensing fees while increasing the profit-sharing proportion; if clients prefer to clarify initial costs and avoid subsequent profit-sharing pressures, they can increase the proportion of one-time licensing fees and reduce the profit-sharing proportion, flexibly adjusting to meet different clients’ financial planning and cooperation demands.Q: How is the competitive landscape of the domestic customized AI chip market, and what are the company’s barriers?A: The competitive landscape of the domestic customized AI chip market shows a “differentiation by field” characteristic, with significant differences in competition intensity and market dominance across different sub-tracks. In the NPU (Neural Processing Unit) field, the company holds an absolute dominant position, as other manufacturers have significant gaps in IP accumulation, technological maturity, and depth of client cooperation, and have not formed competitive forces that threaten the company’s position. However, after the company secures the NPU project contract, it does not undertake the entire industry chain work alone. To optimize supply chain costs and ensure price competitiveness, it usually subcontracts some non-core links (such as basic packaging and auxiliary module design) to other manufacturers, integrating industry resources to achieve “overall cost optimization.” In the VPU (Video Processing Unit) field, market competition is relatively sufficient, and the company’s technical barriers (moat) are not high, as many manufacturers in the industry have the capability to design and supply VPU chips. Therefore, the company may either win total package projects based on experience advantages or participate in subcontracting work for other manufacturers’ total package projects, resulting in a more balanced competitive landscape. The company’s core barriers mainly lie in two aspects: first, the deep moat of IP, having laid out customized AI chip IP about 10 years ahead of peers, leading in market share, and having participated in establishing multiple industry technical standards during previous collaborations with core clients such as mobile manufacturers and automotive companies. Subsequently, domestic clients developing NPUs (whether for video modalities or neural networks) generally need to comply with these established standards, and the company’s products are highly compatible with these standards; second, user habit binding. Other manufacturers wishing to compete must first establish entirely new standards, which must be more aligned with user habits than the company’s existing standards to gain market recognition, significantly raising the competitive threshold in the industry.Q: What are the characteristics of the company’s NPU chip compatibility? How does it compare to international leading companies?A: The compatibility characteristics of the company’s NPU chips need to be analyzed from the dimensions of “scenario adaptation” and “ecological support,” and the comparison with international leading companies should focus on domestic market positioning. From the perspective of scenario compatibility, the company’s NPU chips are characterized by “customization”—each chip is developed for specific business scenarios of clients, only adapting to the computational needs within that scenario. For example, an NPU customized for a client’s intelligent recommendation business optimizes computations related to recommendation algorithms; if the client’s subsequent business direction changes (such as shifting to video generation), this chip will no longer be applicable. This “scenario exclusivity” design approach reduces cross-scenario compatibility but significantly enhances computational efficiency within a single scenario. From the perspective of ecological support compatibility, the company’s NPU chips perform well in industry chain collaboration. For instance, when used with CPUs, they can achieve stable data interaction with mainstream x86 and ARM architecture CPUs. In the AI computing ecosystem, if clients adopt the “NVIDIA GPU training + company’s NPU inference” model, the company’s NPU can perfectly undertake model deployment after GPU training, with no significant bottlenecks in data transmission and model adaptation. Compared to international leading companies (such as NVIDIA and Google), the company’s NPU has gaps in cross-scenario universality and global ecological coverage, but in terms of compatibility and adaptability in specific domestic scenarios, it is not inferior to other domestic manufacturers, especially in collaboration with existing systems of domestic clients (such as self-developed servers and localized algorithm frameworks), and may even have advantages due to being more aligned with domestic client needs, overall placing it in the “first tier domestically, focusing on scenario-based competition” level.Q: Does chip architecture have a decisive impact on its universality and specificity? What architectural strategies does the company currently adopt?A: Chip architecture significantly impacts the universality and specificity of chips, but it is not the only decisive factor. The actual role of architecture needs to be comprehensively judged in conjunction with design objectives, industry chain support, application scenarios, and other dimensions. For example, NVIDIA’s CUDA architecture has strong universality due to its complete software ecosystem and instruction set compatibility, adapting to various AI computation needs. In contrast, Google’s TPU uses the Tensor architecture, which is more inclined towards specialized computation. However, Google can leverage design space unrestricted by wafer area and process limitations, along with complete industry chain support (such as self-developed compilers and cloud ecosystems), to create a certain level of universality in its AI chips by adding redundant designs (such as backup arithmetic units). This indicates that architecture is just a foundation, and the final universality/specificity must be determined by “architecture + design strategy + ecological support” working together. The company’s current architectural strategy focuses on “scenario specialization,” primarily using the Tensor architecture to develop VPU products—clearly not pursuing general adaptability from the outset, but optimizing the computational units and data paths of the Tensor architecture for core scenarios such as video processing and graphics rendering. For example, it strengthens hardware modules related to video encoding/decoding and image denoising while weakening general computational functions unrelated to video scenarios, thereby enhancing the VPU’s energy efficiency and computational speed in specific scenarios, aligning with the company’s positioning as a “customized chip service provider.”Q: What is the progress of Google’s AR project? What were the main reasons for not continuing the project?A: The AR glasses project in collaboration with Google has a clear timeline and termination reasons, with the core issue not lying in chip technology. The project was officially launched in 2022, with both parties clearly aiming to develop core chips for consumer-grade AR glasses. The project progressed smoothly in the early stages: the company completed chip design and cooperated with Google for small-scale sample production, with internal trials at Google showing that the chip met expectations in terms of energy consumption and weight (AR glasses require extremely low power consumption and miniaturization). There were no issues with technical performance not meeting standards. However, the project ultimately did not enter large-scale advancement, with the core reason being that the external design did not meet market demands: first, the external materials of the AR glasses (such as frame materials and display lenses) failed to balance “comfort” and “durability,” with feedback from trials highlighting issues like “pressure on the nose during prolonged wear” and “lens wear and tear”; second, the performance of the camera module was insufficient, as AR glasses need to use cameras for environmental perception and gesture recognition, but the accompanying camera at that time produced blurry images in low-light conditions, and the gesture recognition accuracy did not meet commercial standards. Additionally, the application scenarios for AR glasses were limited—at that time, the consumer-grade AR application ecosystem was not mature, lacking core applications to drive user purchases. Coupled with the external device issues, Google ultimately decided to pause project iteration, not due to the company’s chip technology not meeting standards.Q: What is the current profitability level of the company’s design and mass production businesses?A: There are significant differences in profitability levels between the company’s design and mass production businesses, both of which have clear improvement expectations and need to be broken down by phase and business. In terms of design business, profitability levels gradually improve with product iterations: currently, the first-generation product design business bears a large amount of initial R&D investment (such as personnel salaries, equipment procurement, and technical validation costs), and after deducting these expenses, it can barely maintain breakeven, with almost no excess profit. However, for second and third-generation products, as the technical solutions become relatively mature and the reuse rate of R&D increases (for example, some IP modules can be directly reused), costs significantly decrease, with net profit margins typically reaching 3%. As the reuse rate of mature solutions by clients further increases (for example, sharing basic design frameworks among different clients in the same industry), future net profit margins are expected to continue rising to around 5%. In terms of mass production business, profitability levels need to distinguish between “nominal gross profit” and “actual gross profit”: the nominal gross profit margin of mass production business is about 50% of the client’s mass production revenue (i.e., if a client’s chip mass production revenue is 100 million RMB, the company’s mass production revenue is about 50 million RMB), but after deducting costs paid to wafer fabs, packaging, and testing factories (such as wafer procurement costs and packaging/testing service fees), the actual gross profit margin drops to around 25%. In the future, as the number of clients increases (scale effects reduce unit management costs) and supply chain bargaining power improves (such as signing long-term agreements with wafer fabs to lower procurement prices), the actual gross profit margin of mass production business is expected to rise above 30%. The overall profitability levels of both design and mass production businesses will further optimize with scale expansion.———————-
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