SPI: Serial Peripheral Interface, is a synchronous serial interface for device communication.
SPI was developed by Motorola around 1985 and is suitable for short-distance, device-to-device communication.
Since then, this interface has become a de facto standard adopted by many semiconductor manufacturers, especially microcontrollers (MCUs) and microprocessors (MPUs).
The SPI bus is a 4-wire bus, typically with one master device and one or more slave devices, requiring at least 4 wires, although 3 can also suffice.
MOSI: Master Output Slave Input, data output from the master device to the slave device;
MISO: Master Input Slave Output, data input to the master device from the slave device;
SCLK: Serial Clock, clock signal generated by the master device;
SS: Slave Select, signal to select the slave device, controlled by the master device;
The SS signal above can also be understood as the CS signal, generally active low, hence also referred to as NSS (Not Select) signal;
CS: Chip Select, signal to enable/select the slave device, controlled by the master device;
The most basic SPI communication is one master and one slave, for example: an STM32 as the master and a W25Q16 (SPI Flash) as the slave. SPI communication can also occur between two MCUs.
The above example shows the master sending one byte of data (0x53), and the slave responding with one byte of data (0x46).
One Master Multiple Slaves
SPI can be configured as one master and one slave (one master device and one slave device), but it can also be one master and multiple slaves. There are two common connection methods for one master multiple slaves.
Typically, each slave requires a separate SS line. To communicate with a specific slave, set that slave’s SS line to low while keeping the others high.
Some applications only require one NSS (for example: shift registers). In this layout, data is shifted from one slave device to another.
SPI communication is relatively simple, with one clock transmitting one bit of data (master -> slave, or slave -> master).
Theoretically, the SPI clock frequency can be very high, generally ranging from several MHz to hundreds of MHz. For example, the common W25Q16 supports a maximum SPI frequency of 80MHz.
The SPI communication rate must be combined with actual conditions and cannot exceed the maximum clock frequency supported by the master or slave.
SPI data flows in two directions:
One “disadvantage” of SPI communication is that there is no designated flow control and no acknowledgment mechanism to confirm whether data has been received.
This means: it is unclear when the master sends data to the slave, when the slave sends data to the master, and exactly how many bytes of data should be sent.
At this point, the master and slave that need to communicate must reach an agreement, generally with the master controlling the read and write operations.
For example, the operation of reading and writing data to the SPI Flash is as follows:
The first byte is the instruction, followed by 3 bytes (24 bits) of address, all sent from the master to the slave. Afterwards, the master reads the data sent from the slave.
In addition to setting the clock frequency, the master must also configure the clock polarity and phase related to the data.
CPOL determines the clock polarity, which can be inverted using a simple inverter.
CPHA determines the timing of the data bits relative to the clock pulse (i.e., the phase).
Generally, processors with integrated SPI peripherals have SPI-related configuration registers. For STM32, the reference manual provides detailed information about SPI configuration.
It is recommended to understand this in conjunction with timing diagrams, rather than memorizing it.
Author: strongerHuang, Source: strongerHuang
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