
The era of general-purpose processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric artificial intelligence (AI) applications, edge computing, automotive, and industrial market applications continue to expand, they are driving a fundamental shift in processor design.
It can be said that chip manufacturers are no longer relying on general architectures to meet the demands of these specialized markets. Open ecosystems like RISC-V allow silicon developers to create custom solutions that provide both innovation and design efficiency, unlocking new opportunities for a variety of applications.
RISC-V, as an open instruction set architecture (ISA), is rapidly gaining momentum due to its scalability and royalty-free licensing. Rich Wawrzyniak, chief analyst at SHD Group, stated, “RISC-V SoC shipments are expected to grow at nearly 47% CAGR, capturing nearly 35% of the global market by 2030.” This growth underscores why SoC designers are increasingly embracing architectures that offer greater flexibility and specialization.

Figure 1: NVIDIA’s RISC-V core and extended view: a unified architecture with dozens of applications and billions of processors.

Figure 2: META’s MTIA accelerator integrates Andes RISC-V cores to optimize AI performance.

Figure 3: An example of a hardware/software co-design flow for developing and optimizing custom instructions.

Figure 4: Ace and Copilot simplify the development and integration of custom instructions.
The Andes Custom Extension (ACE) framework and Copilot toolchain provide a streamlined path for RISC-V customization. ACE enables developers to create custom instructions optimized for specific workloads and supports advanced features such as pipelined execution, custom registers, and memory structures.
Copilot automates the integration process by regenerating the entire hardware and software stack, including RTL, compilers, debuggers, and simulators, based on defined extensions. This reduces manual effort, ensures consistency between hardware and software, and accelerates development cycles, providing customized RISC-V design utility for a wide range of teams and applications.
Source: Excerpt from the RISC-V International Association
