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1. Problem Description
Performing a large number of complex operations during CAN interrupt data reception can indeed lead to long execution times for the Interrupt Service Routine (ISR).
This may cause issues such as missing other interrupt requests and affecting the real-time performance of the system.
Since the ISR should complete as quickly as possible to ensure the system can respond to other important events in a timely manner.
2. Solutions
(1) Flag and Buffer Mechanism
When the beginning of a CAN data frame (frame header) is received in the interrupt, set a flag to indicate that data reception has started, and then simply store the received data into a buffer (which can be an array).
When the frame tail is received, set another flag to indicate that reception has ended. In the main program loop, check these flags, and when the reception complete flag is set, perform complex operations such as frame header and tail validation, checksum checks, and data conversion assignments on the buffered data. This allows the ISR to return quickly, reducing interrupt latency.
(2) Hardware-Supported Filtering Mechanism
If the CAN controller supports hardware filtering, make full use of this feature. By setting appropriate filter masks and filters, allow the CAN controller to filter out unnecessary message frames at the hardware level, only receiving frames that meet specific conditions (such as a specific frame ID range). This can reduce the amount of data entering the ISR, thereby decreasing interrupt processing time.
(3) Optimize Data Processing Algorithms
Optimize the algorithms for frame header and tail validation and checksum checks. For example, use more efficient lookup algorithms to determine frame headers and tails; for checksum calculations, if a simple method (like parity check) is used, it can be quickly completed through bit manipulation; if a complex checksum (like CRC check) is used, consider using a pre-computed lookup table to speed up the verification process.
(4) Improve Processor Performance or Adopt Multi-Core Architecture (if possible)
Upgrading the processor or choosing a higher-performance processor can shorten the execution cycle of each instruction, thereby reducing interrupt processing time to some extent. If the system supports a multi-core architecture, some non-critical processing tasks (such as data conversion assignments) can be allocated to other cores, alleviating the burden on the interrupt handling core.
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Original link:
https://blog.csdn.net/weixin_60324241/article/details/143754967