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1. First of all, UART and TTL are completely different concepts.
UART stands for Universal Asynchronous Receiver/Transmitter, which is a serial asynchronous communication protocol.
The TTL level signal specifies that +5V is equivalent to logic “1” and 0V is equivalent to logic “0” (when using binary to represent data). This method of data communication and level specification is known as the TTL (Transistor-Transistor Logic) signal system. It is the standard technology for communication between various parts of devices controlled by computer processors.
The full name of TTL integrated circuits is Transistor-Transistor Logic integrated circuits, which mainly include five series: 54/74 standard TTL, high-speed TTL (H-TTL), low-power TTL (L-TTL), Schottky TTL (S-TTL), and low-power Schottky TTL (LS-TTL).
In simple terms, UART, SPI, IIC, etc. can be classified as one category, while TTL, RS232, RS485, etc. can be classified as another. In fact, RS232 and RS485 are more complex than TTL, as the former are standards for serial data communication interfaces, while TTL is merely a level standard.
2. This vague concept is not easy to understand, so let’s look at actual signals.
Taking the CP2102 USB UART Board as an example, we will use the most common serial configuration: 9600 8N1 (9600 baud rate, 8 data bits, no parity bit, 1 stop bit) to send 1 byte 0xAA.
At a baud rate of 9600, the theoretical duration of 1 bit is 1/9600 = 104.166us, and the actual measured time is 103.333us.
Interpreting UART signals
As a type of asynchronous serial communication protocol, UART works by transmitting each character of data one bit at a time.
The meanings of the bits are as follows:
Start bit: A logic “0” signal is sent first, indicating the start of the character transmission.
Data bits: Following the start bit, the number of data bits can be 4, 5, 6, 7, or 8, forming a character. ASCII code is typically used. Transmission starts from the least significant bit, synchronized by the clock.
Parity bit: This bit, added to the data bits, ensures that the number of “1” bits is even (even parity) or odd (odd parity), thus verifying the correctness of the data transmission.
Stop bit: This is a character data end marker. It can be 1, 1.5, or 2 bits of high level. Since data is timed on the transmission line, and each device has its own clock, there may be slight desynchronization between two devices during communication.
Therefore, the stop bit not only indicates the end of transmission but also provides an opportunity for the computer to correct clock synchronization. The more stop bits used, the greater the tolerance for clock desynchronization, but the data transmission rate will also be slower.
Idle bit: In a logic “1” state, indicating that there is currently no data being transmitted on the line.
The received 8-bit data is 0101 0101, as the least significant bit is transmitted first, converting it to 1010 1010 => 0xAA.
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Original link:
https://blog.csdn.net/u014197096/article/details/107905848