Cortex Authority Manual – Floating Point Operations

Floating Point Representation

The representation of floating-point numbers follows the IEEE 754 standard, including single precision, double precision, and half precision floating-point numbers. Each floating-point number has a sign bit, an exponent, and a fraction part.

Single Precision Floating Point (32 bits)

  • Bit 31: Sign bit (0 indicates positive, 1 indicates negative).

  • Bits 30-23: Exponent part, a total of 8 bits.

  • Bits 22-0: Fraction part, a total of 23 bits.

Special Cases:

  • NaN (Not a Number): When the exponent part is all 1s and the fraction part is not 0, it represents NaN.

    • Signaling NaN: Bit 22 is 0, and the remaining bits of the fraction are non-zero.

    • Quiet NaN: Bit 22 is 1, and the remaining bits of the fraction can be any value.

Half Precision Floating Point (16 bits)

  • Bit 15: Sign bit (0 indicates positive, 1 indicates negative).

  • Bits 14-10: Exponent part, a total of 5 bits.

  • Bits 9-0: Fraction part, a total of 10 bits.

Special Cases:

  • NaN (Not a Number): When the exponent part is all 1s and the fraction part is not 0, it represents NaN.

    • Signaling NaN: Bit 9 is 0, and the remaining bits of the fraction are non-zero.

    • Quiet NaN: Bit 9 is 1, and the remaining bits of the fraction can be any value.

Double Precision Floating Point (64 bits)

  • Bit 63: Sign bit (0 indicates positive, 1 indicates negative).

  • Bits 62-52: Exponent part, a total of 11 bits.

  • Bits 51-0: Fraction part, a total of 52 bits.

Special Cases:

  • NaN (Not a Number): When the exponent part is all 1s and the fraction part is not 0, it represents NaN.

    • Signaling NaN: Bit 51 is 0, and the remaining bits of the fraction are non-zero.

    • Quiet NaN: Bit 51 is 1, and the remaining bits of the fraction can be any value.

Floating Point Unit (FPU)

The Floating Point Unit (FPU) supports double precision data calculations, floating-point remainders, integer and floating-point conversions, and more. The FPU can be enabled or disabled through the SCB->CPACR register.

  • SCB->CPACR: Used to control access permissions for coprocessors, including the FPU.

Floating Point Registers and Control Registers

Floating Point Status and Control Register (FPSCR)

The FPSCR is used to control and indicate the status of floating-point operations, including the following bits:

  • N (Negative): Negative result flag.

  • Z (Zero): Zero result flag.

  • C (Carry): Carry flag.

  • V (Overflow): Overflow flag.

  • Q (Inexact): Inexact result flag.

  • AHP (Alternating Half Precision): Alternating half precision control bit.

  • DN (Default NaN): Default NaN mode control bit.

  • FZ (Flush to Zero): Flush to zero mode control bit.

  • RMode (Rounding Mode): Rounding mode control bit.

  • IDC (Input Denormal Cumulative): Input denormal cumulative exception bit.

  • IXC (Inexact Cumulative): Inexact cumulative exception bit.

  • UFC (Underflow Cumulative): Underflow cumulative exception bit.

  • OFC (Overflow Cumulative): Overflow cumulative exception bit.

  • DZC (Divide-by-Zero Cumulative): Divide-by-zero cumulative exception bit.

  • IOC (Invalid Operation Cumulative): Invalid operation cumulative exception bit.

Floating Point Context Control Register (FPCCR)

The FPCCR controls the operation of the floating-point context, including the following bits:

  • LSPACT (Lazy State Preservation Active): Lazy state preservation active flag. If set, it indicates that the current exception handling has been interrupted and requires a floating-point context push operation.

Floating Point Context Address Register (FPCAR)

The FPCAR stores the address of the floating-point context, used to save the values of floating-point registers during exception handling.

Floating Point Default Status Control Register (FPDSCR)

The FPDSCR is used to control the default state of floating-point operations, including rounding modes, etc.

Media and Floating Point Feature Registers (MVFRO and MVFR1)

These registers provide information about the features and supported functionalities of the floating-point unit.

Lazy Stack Preservation

Lazy stack preservation is an optimization mechanism used to reduce the overhead of stack operations during exception handling:

  • Without Lazy Stack Preservation: Each exception handling requires pushing 25 registers onto the stack, resulting in an increase of 29 cycles in exception handling time.

  • With Lazy Stack Preservation: The exception handling time remains at 12 clock cycles (for a zero-wait state memory system), significantly improving performance.

Related Registers and Bits

  • FPCA Bit in CONTROL Register: Indicates whether floating-point operation capability is present.

  • Bit 4 of EXC_RETURN: Indicates whether it is a long stack frame or a short stack frame.

  • LSPACT Bit in FPCCR: Indicates whether exception handling requires a stack operation.

Floating Point Exceptions

Floating point exceptions are indicated by the flags in the FPSCR:

  • IDC (Input Denormal Cumulative): Input denormal cumulative exception.

  • IXC (Inexact Cumulative): Inexact cumulative exception.

  • UFC (Underflow Cumulative): Underflow cumulative exception.

  • OFC (Overflow Cumulative): Overflow cumulative exception.

  • DZC (Divide-by-Zero Cumulative): Divide-by-zero cumulative exception.

  • IOC (Invalid Operation Cumulative): Invalid operation cumulative exception.

These exceptions can be used for debugging and optimizing floating-point operation code.

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