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1.
How does a rock turn into a chip?
How can a piece of ordinary quartzite be transformed into a chip worth its weight in gold?
The first step in processing this rock is from purification to transformation. First, the quartzite is crushed into sand, then subjected to high-temperature smelting and chemical refining, ultimately yielding a nearly 100% pure single crystal silicon ingot. This silicon column weighs several hundred kilograms and is then sliced into wafers with a diameter of 300 millimeters and a thickness of only 0.75 millimeters. The surface of the wafer must be polished to a mirror-like finish, with a deviation controlled within 0.1 nanometers, and the back must be engraved with a unique serial number, leaving a small notch for orientation; otherwise, subsequent machines won’t know where to start.
At this point, we are still only at the raw material preprocessing stage. To manufacture a high-end CPU, hundreds of machines and thousands of processes are required. Moreover, the cleanliness of the workshop is hundreds of times better than that of an operating room. A single speck of dust, invisible to the naked eye, falling on the wafer could short-circuit one of the billions of transistors, rendering the entire chip useless. Therefore, even at this stage, perfect wafers are still rare, which is why chips are graded: the piece with the fewest defects on the wafer is used for the top-tier i9; slightly worse ones are used for i7 and i5; those with flaws but still usable are made into i3. Different grades correspond to different prices.
If you magnify the chip 100,000 times, you will find that it is not a flat board but a multi-layered micro skyscraper. The residents of this building are transistors. For example, a 5nm process transistor measures only 36×6×52 nanometers, with a distance of just 57 nanometers between two transistors, thinner than one ten-thousandth of a hair, and even smaller than mitochondria in cells. This building must have over a hundred layers, with each layer consisting of alternating metal wires and insulators, and the connections between layers must be precisely aligned; any error could ruin the entire structure.
The builders of this skyscraper are photolithography machines. They are somewhat like the photo development toys we played with as children, but the precision and difficulty are off the charts. First, a photomask is needed, which contains the designed circuit patterns, with lines thinner than one ten-thousandth of a hair. However, the finer the lines, the more special the light required. Ordinary light wavelengths are too long to engrave such fine patterns, so engineers must create their own light.
First, in a vacuum environment, a beam of light 15 times stronger than that used for cutting metal is used to strike the molten metal tin droplets. The moment the tin droplets are hit, they vaporize into plasma, releasing extremely short-wavelength EUV (extreme ultraviolet light). However, this light is absorbed upon contact with air, so the interior of the photolithography machine must maintain absolute vacuum and use special mirrors to guide it. The difficulty of directing this light precisely onto the wafer is akin to launching a laser from the moon to hit a specific person’s fingertip on Earth.
Having light is not enough; a photosensitive coating is also needed, known as photoresist. First, a uniform layer of photoresist is applied to the wafer’s surface, dried to remove impurities, and then sent into the photolithography machine. The EUV light passes through the pattern on the photomask and illuminates the photoresist; the exposed areas will automatically fall off, while the unexposed areas remain firmly attached to the wafer. Next, the wafer is immersed in an etching solution, where the silicon areas not protected by the photoresist will be etched out, leaving the initial form of a circuit.
However, silicon itself has average conductivity, so copper must be plated into the grooves—but it cannot be plated directly; a barrier layer must first be added to prevent copper atoms from penetrating the silicon and causing damage. Once the grooves are filled with copper, they are repeatedly rinsed with ultra-pure water and dried with nitrogen to avoid residual dust causing transistor short circuits; only then is this layer considered truly complete. But it is still early; the chip has over a hundred layers of circuitry, and this entire process must be repeated over a hundred times, with precision maintained at every step.
2.
How is yield calculated?
In the foundry industry, the yield of mature processes has long been a key factor. Take SMIC, for example; its 28nm process yield has reached 94-96%, firmly establishing its position in the mid-to-low-end foundry market; even the 14nm process yield has surpassed 90%, making mass production of domestic AI training chips feasible.
However, in advanced processes, the yield differences can significantly separate companies. TSMC’s 2nm (N2) process mass production yield has exceeded 70%, with some customers reporting yields close to 75%. Thanks to this, top clients like Apple and NVIDIA are scrambling to place orders, with production capacity already booked until 2027. In contrast, Samsung, while claiming an SF2 process yield of “85%”, has an actual mass production average yield of only 40% to 50%, making the gap with TSMC glaringly obvious.
Switching from FinFET to GAA represents a significant structural change in transistors, with all three manufacturers feeling their way through the process. TSMC, having previously excelled with FinFET technology, is leading in yield. Recent news indicates that N2 yield is approaching 80%. Intel’s 18A process (around 50%-55%) attempted to shortcut through back-side power supply technology, but this has made yield improvement more challenging. Samsung’s SF2 (around 40%) is still grappling with the tough challenges of GAA technology.
While EUV has improved precision, the photons are scarce and highly random, leading to rough edges, making chips below 2nm prone to issues. This can only be controlled through the process, and every company has its own challenges. SMIC, lacking EUV lithography machines, has managed to achieve an equivalent 7nm process using DUV multiple exposures, which is a significant breakthrough. However, it requires many exposures, increasing the process by 30% and costs by 50%.
|
Manufacturer |
Yield Situation |
|
SMIC-28nm |
Yield stabilizes at94%-96%, with the gap to industry-leading levels narrowed to3 percentage points, leading in monthly production capacity and global market share. |
|
SMIC-14nm |
Yield exceeds90%, capable of stable mass production to meetAI training chip and other mid-to-high-end demands. |
|
TSMC-N2(2nm) |
Mass production yield exceeds70%, far ahead, securing orders from almost all top clients like Apple, NVIDIA, and AMD, with production capacity booked until2027. |
|
Samsung-SF2(2nm) |
Actual mass production average yield is about40%-50%, far below TSMC. |
The area of the chip will always affect the yield; the larger the area, the lower the yield. Therefore, when discussing yield, it is essential to consider the specific type of chip: TSMC can achieve yields over 90% for small area SRAM test chips; however, for large AI chips like those from NVIDIA, which exceed 800mm², the yield will certainly drop significantly, with 30% being considered a high point.
In the industry, yield (defect density) is calculated using statistical models, and currently, four have evolved.
(1) Poisson Model
The Poisson model is the basic assumption of random defect distribution, with the calculation formula:
Where, is the defect density (defects/cm²), is the chip area (cm²). The probability of having defects in a unit area is , and when defects occur, the chip fails, so the yield is the probability of no defects.
This method is quite old, originating in the late 1960s.
Applicable in two scenarios:
1. Small to medium area chips, such as CPUs and mobile processors:
For Intel’s 18A process, when the theoretical yield of a 114mm² (1.14cm²) chip is= , there is a discrepancy with the actual measured yield of 64.4% because this model is insensitive to edge defects, as Poisson assumes defects are uniformly randomly distributed on the wafer.
2. Mature processes can also be validated:In the early stages of TSMC’s N7 process, the Poisson yield for a 200mm² chip is= , close to the actual mass production level.
This statistical strategy is overly optimistic; it does not consider the concentration effect of edge defects, which is certainly not applicable for large chips.
(2) Murphy Model
The Murphy model is a correction for these edge defects, proposed in the late 1980s. It assumes that defect density follows a symmetric triangular distribution, with a mean of , and the yield calculation formula is:
This method uses an integral triangular distribution to correct the higher defect density at the wafer edges compared to the center. It is suitable for large-sized chips (GPU, AI): For NVIDIA’s H100 chip with an area of 814mm² (8.14cm²), the yield calculated using the Murphy model is , while the mass production yield is 65%, which is still close.
This model better reflects the situation in production where edge defect rates are higher, meaning that the defect density at the wafer edges is usually 30%-50% higher than at the center.
(3) Seed Model
Assuming that defect density follows an exponential distribution, the yield calculation formula is:When defects cluster locally, it may be due to process issues such as uneven film deposition, leading to the Seed model, which first appeared in the mid-1990s.
Two application scenarios:
1. Memory chipsIn Samsung’s 3nm SRAM manufacturing, the defect density is defects/cm², for a chip area of 100mm² (1cm²), the Seed model predicts the yield as: The measured yield is 85%, which is quite accurate.2. Power devices
The defects in silicon carbide MOSFETs are due to dislocation clustering in the epitaxial layer. The traditional Poisson model assumes defects are independently and randomly distributed, while the Seed model considers the defect clustering effect, predicting yields that are usually 10-15% lower than the Poisson model.
The problem with this model is that it has strict assumptions about defect distribution, requiring historical data to verify the applicability of the exponential distribution, and it does not consider the impact of lithography defects on subsequent etching, which belongs to defect propagation between process steps.
(4) Bose-Einstein Model
Assuming defects concentrate on a critical mask layer (such as the transistor gate layer), the yield calculation formula is:This model considers quantum tunneling effects and emerged in the early 2010s. In advanced processes, the probability of defects in critical layers increases exponentially as dimensions shrink.
Applicable scenarios::
1. GAA architecture transistorsIn TSMC’s N2 process GAA nanosheet layer, if , the Bose-Einstein yield for a 100mm² chip (1cm²) is , consistent with the actual initial yield of 60%.2. Extreme ultraviolet lithography (EUV) processThe single-exposure defect rate of ASML’s NXE:3400B lithography machine in critical layers follows Bose-Einstein statistical characteristics, with a predicted error of less than 5%.
| Model | Mathematical Assumption | Applicable Scenarios | Prediction Error Range | Industry Cases |
|---|---|---|---|---|
| Poisson Model | Defects independently randomly distributed | Small to medium chips, mature processes | ±10%-15% | Intel’s 18A process early measurements |
| Murphy Model | Edge defects triangular distribution | Large chips, early advanced processes | ±5%-8% | TSMC N2 process SRAM test |
| Seed Model | Defect clustering exponential distribution | Memory chips, power devices | ±8%-12% | Samsung 3nm SRAM mass production |
| Bose-Einstein Model | Critical layer defect quantum distribution | GAA architecture, EUV process | ±3%-6% | TSMC N2 process GAA transistors |
Let’s also talk about the new rare earth export regulations on October 9.
3.
New Rare Earth Export Regulations on October 9
On October 9, 2025, the Ministry of Commerce of China issued two announcements regarding rare earth export controls, stating that starting from December 1, any foreign magnets and semiconductor materials containing 0.1% or more of Chinese heavy rare earth components must obtain approval from the Chinese side before re-export.
No one expected that a tiny rare earth atom could put the world’s top semiconductor giants in a dilemma. After the new rare earth export regulations come into effect, TSMC’s 5nm chip production suddenly hit a snag, as its core material lanthanum’s purity requirement exceeds the control standard by 0.5 percentage points. To continue mass production, it must first pass the mainland’s licensing approval. Rare earths are quite critical in high-end manufacturing. For instance, lanthanum is used in the atomic deposition process of the gate layer in 5nm chips, enhancing electron mobility by 20%, increasing transistor switching speed by 15%, and reducing chip leakage current to an astonishing 1/11 billion amperes. For TSMC, each wafer worth $15,000 requires only 2.3 milligrams of lanthanum. The mainland can stably supply lanthanum with a purity of 99.9999%, while Japan can only reach 99.99%. This slight difference can lead to a 3 percentage point drop in chip yield, which is a critical line in the semiconductor industry.
The global production of high-purity lanthanum is dominated by the mainland, accounting for 87% of the absolute share, with the remaining 13% controlled by a French company, whose raw materials still need to be imported from China’s Baotou rare earth mine. Moreover, lanthanum must be transported under inert gas protection; once it contacts air, it oxidizes and becomes waste. The shipping route from Baotou to Kinmen and then to Taiwan is the most cost-effective and purity-assured option. If forced to switch to a Japanese transit route, transportation costs would soar fivefold, and purity would further decline due to multiple transfers. TSMC’s call for “de-Mainlandization” essentially means abandoning the most stable supply chain, akin to cutting off its own lifeline.
This export control sets the purity standard for lanthanum at 99.999%, while TSMC’s 5nm process requires 99.9995%. To compensate for this slight purity difference, an additional 18 refining processes are needed. The Semiconductor Industry Association of America has calculated that just redesigning the compatible processes would cost over $4 billion. Ironically, 80% of the core patents for these alternative processes are held by the Chinese Academy of Sciences, making it impossible to bypass.
In addition to TSMC’s 5nm process being stalled due to the shortage of high-purity lanthanum, giants like Samsung and SK Hynix are also facing supply crises for critical materials such as gallium nitride and germanium. According to Bloomberg, if China fully suspends the export of related materials, global semiconductor capacity could decline by 15%-20%, and the production of some high-end products could be halted for more than six months.