Getting Started with FPGA Programming: A Comprehensive Guide Using Verilog

Getting Started with FPGA Programming: A Comprehensive Guide Using Verilog, published by Tsinghua University Press, foreign book title: Programming FPGAs: getting started with Verilog, authors: Simon Monk (Author), Li Yang (Translator), Bie Zhizong (Translator). Written by electronic circuit master Simon Monk, this book guides you to start using three popular FPGA development boards: Mojo, Papilio One, and Elbert 2. The book is written in a humorous and easy-to-understand language, with clear explanations of examples, and provides downloadable example program source codes and complete .bit files. You will write instructions for a large number of projects from start to finish, including LED decoders, timers, tone generators, and even memory-mapped video displays! This book can serve as a guide for electronics enthusiasts and as an introductory book for professional developers.

Table of Contents

Chapter 1 Logic 11.1 Logic Gates 11.1.1 NOT Gate 21.1.2 AND Gate 31.1.3 OR Gate 31.1.4 NAND and NOR Gates 41.1.5 XOR Gate 51.2 Binary 61.3 Adding Logic 81.4 Flip-Flops 91.5 Shift Registers 111.6 Binary Counters 121.7 Summary 13Chapter 2 FPGA 152.1 How FPGA Works 152.2 Elbert 2 172.3 Mojo 182.4 Papilio 202.5 Software Setup 222.5.1 Install ISE 222.5.2 Install Elbert Software 242.5.3 Install Mojo Software 252.5.4 Install Papilio Software 262.6 Project Files 262.7 Summary 27Chapter 3 Drawing Logic 293.1 Multiplexer Example 293.1.1 Step 1: Create a New Project 303.1.2 Step 2: Create a New Schematic 343.1.3 Step 3: Add Logic Symbols 363.1.4 Step 4: Connect Gates 363.1.5 Step 5: Add IO Markers 373.1.6 Step 6: Create User Constraints File 383.1.7 Step 7: Generate .bit File 423.1.8 Step 8: Program Development Board 443.1.9 Test Results 463.2 A 4-Bit Counter Example 483.2.1 Drawing Schematic 493.2.2 Implementing Constraints File 493.2.3 Testing Counter 523.3 Summary 52Chapter 4 Introduction to Verilog 534.1 Modules 534.2 Wires, Registers, and Buses 544.3 Parallel Execution 544.4 Digital Formats 544.5 Multiplexer Written in Verilog 554.6 Counter Written in Verilog 594.7 Synchronous Logic 624.8 Summary 62Chapter 5 Modular Verilog 635.1 Seven Segment Decoder 635.2 Button Debouncing 685.3 Multiplexing Seven Segment Display and Counter 735.3.1 Project Structure 745.3.2 display_7_seg 765.3.3 counter_7_seg 795.3.4 User Constraints File 815.3.5 Importing Module Source Code 825.3.6 Setting Top-Level Module 825.3.7 3-Digit Version 835.3.8 Testing 835.4 Summary 84Chapter 6 Timer Example 856.1 State Machine 856.2 State Machine Design 876.3 Hardware 886.3.1 What You Need 886.3.2 Build 886.4 Modules 906.5 User Constraints File 916.6 Timer Module 926.6.1 Inputs and Outputs 926.6.2 Button Press 926.6.3 Alarm Instance 936.6.4 Modeling Time and Display 936.6.5 State Machine Implementation 946.6.6 Tasks 966.7 Testing 986.8 Summary 98Chapter 7 PWM and Servo Motors 997.1 Pulse Width Modulation 997.2 PWM Module 1007.2.1 PWM Module Inputs and Outputs 1017.2.2 PWM Testing Module 1017.2.3 Try It Out 1047.3 Servo Motor 1047.4 Hardware 1057.4.1 What You Need 1057.4.2 Build 1067.5 Servo Module 1097.6 Summary 112Chapter 8 Audio 1138.1 Tone Generation 1138.2 Audio Output of Mojo 1158.3 General Audio/Signal Generator 1168.3.1 Tone Module 1168.3.2 tone_tester Module 1188.3.3 Testing 1188.4 Playing Audio Files 1218.4.1 Audio Files 1218.4.2 RAM 1228.4.3 wav_player Module 1228.4.4 Testing 1258.4.5 Prepare Your Own Audio 1258.5 Summary 128Chapter 9 Video 1299.1 VGA 1299.2 VGA Timing Synchronization 1329.3 Drawing Rectangles 1339.3.1 VGA Module 1349.3.2 VGA and Elbert 2 1379.4 Making Objects Move 1389.5 Memory-Mapped Display 1419.6 Summary 143Chapter 10 Additional Content 14510.1 Simulation 14510.2 Deeper Content 14610.3 Cores and Soft Processors 14710.4 More Papilio Content 14710.5 More Mojo Content 14910.6 Summary 150

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